DAC102S085

SNAS364E – MAY 2006 – REVISED MARCH 2013

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A.C. and Timing Characteristics

Values shown in this table are design targets and are subject to change before product release.

specified.

Units

Symbol

Parameter

Conductions

(Limits)

SCLK Frequency

40

30

MHz (max)

100h to 300h code change

4.5

6

µs (max)

SR

Output Slew Rate

1

V/µs

Glitch Impulse

Code change from 200h to 1FFh

12

nV-sec

Digital Feedthrough

0.5

nV-sec

Digital Crosstalk

1

nV-sec

DAC-to-DAC Crosstalk

3

nV-sec

Multiplying Bandwidth

160

kHz

Total Harmonic Distortion

70

dB

input frequency = 10kHz

6

µsec

Wake-Up Time

39

µsec

SCLK Cycle Time

25

33

ns (min)

SCLK High time

7

10

ns (min)

SCLK Low Time

7

10

ns (min)

SYNC Set-up Time prior to SCLK

4

10

ns (min)

Falling Edge

Data Set-Up Time prior to SCLK Falling

1.5

3.5

ns (min)

Edge

Data Hold Time after SCLK Falling

1.5

3.5

ns (min)

Edge

SCLK fall prior to rise of SYNC

0

3

ns (min)

SYNC High Time

6

10

ns (min)

(1)

Quality Level).

(2)

This parameter is specified by design and/or characterization and is not tested in production.

6

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