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ADS42LB69IRGC25 Arkusz danych(PDF) 10 Page - Texas Instruments |
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ADS42LB69IRGC25 Arkusz danych(HTML) 10 Page - Texas Instruments |
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10 / 80 page  ADS42LB49 ADS42LB69 SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com TIMING REQUIREMENTS: QDR LVDS Mode (1) (2) Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave input clock, CLOAD = 3.3 pF (3), and R LOAD = 100 Ω (4), unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, and DRVDD = 1.7 V to 1.9 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSU Data setup time(5)(6) Data valid to DxCLKP, DxCLKM zero-crossing 0.23 0.31 ns DxCLKP, DxCLKM zero-crossing to data becoming tH Data hold time(5)(6) 0.16 0.29 ns invalid LVDS bit clock duty cycle Differential bit clock duty cycle (DxCLKP, DxCLKM) 50% Input clock rising edge cross-over to output frame clock tPDI Clock propagation delay 7 10.1 13 ns (DxFRAMEP-DxFRAMEM) rising edge cross-over tRISE, Data rise and fall time Rise time measured from –100 mV to +100 mV 0.18 ns tFALL tCLKRISE, Output clock rise and fall time Rise time measured from –100 mV to +100 mV 0.2 ns tCLKFALL (1) Measurements are done with a transmission line of 100- Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (2) Timing parameters are ensured by design and characterization and are not tested in production. (3) CLOAD is the effective external single-ended load capacitance between each output pin and ground. (4) RLOAD is the differential load resistance between the LVDS output pair. (5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV. (6) The setup and hold times of a channel are measured with respect to the same channel output clock. Table 4. QDR LVDS Timings at Lower Sampling Frequencies CLOCK PROPAGATION SETUP TIME (ns) HOLD TIME (ns) DELAY (ns) tSU tHO tPDI SAMPLING FREQUENCY (MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX 80 1.06 1.21 0.84 1.29 6 9.3 12 120 0.63 0.77 0.66 0.88 7 9.5 13 160 0.43 0.55 0.39 0.61 7 9.7 13 200 0.31 0.42 0.28 0.47 7 9.8 13 230 0.24 0.34 0.17 0.36 7 9.9 13 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 |
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