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ADC574AKP Arkusz danych(PDF) 9 Page - Burr-Brown (TI) |
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ADC574AKP Arkusz danych(HTML) 9 Page - Burr-Brown (TI) |
9 / 10 page 9 ® ADC574A desired. When 12/8 is high, all 12 output lines (DB0–DB11) are enabled simultaneously for full data word transfer to a 12-bit or 16-bit bus. In this situation the AO state is ignored. When 12/8 is low, the data is presented in the form of two 8-bit bytes, with selection of the byte of interest accom- plished by the state of AO during the read cycle. Connection of the ADC574A to an 8-bit bus for transfer of left-justified data is illustrated in Figure 8. The AO input is usually driven by the least significant bit of the address bus, allowing storage of the output data word in two consecutive memory locations. READING OUTPUT DATA After conversion is initiated, the output data buffers remain in a high-impedance state until the following four logic conditions are simultaneously met: R/C high, STATUS low, CE high, and CS low. Upon satisfaction of these conditions the data lines are enabled according to the state of inputs 12/8 and AO. See Figure 7 and Table V for timing relation- ships and specifications. In most applications the 12/8 input will be hard-wired in either the high or low condition, although it is fully TTL- and CMOS-compatible and may be actively driven if SYMBOL PARAMETER MIN TYP MAX UNITS Convert Mode tDSC STS Delay from CE 60 200 ns tHEC CE Pulse Width 50 30 ns tSSC CS to CE Setup time 50 20 ns tHSC CS low during CE high 50 20 ns tSRC R/C to CE setup 50 0 ns tHRC R/C low during CE high 50 20 ns tSAC AO to CE setup 0 ns tHAC AO valid during CE high 50 20 ns tC Conversion time, 12-bit cycle 15 20 25 µs 8-bit cycle 10 13 17 µs Read Mode tDD Access time from CE 75 150 ns tHD Data valid after CE low 25 35 ns tHL Output float delay 100 150 ns tSSR CS to CE setup 50 0 ns tSRR R/C to CE setup 0 ns tSAR AO to CE setup 50 25 ns tHSR CS valid after CE low 0 ns tHRR R/C high after CE low 0 ns tHAR AO valid after CE low 50 ns tHS STS delay after data valid 300 400 1000 ns NOTE: Specifications are at +25 °C and measured at 50% level of transitions. TABLE V. Timing Specifications. FIGURE 7. Read Cycle Timing. FIGURE 6. Conversion Cycle Timing. CE t HEC t SSC t SRC t HSC t HRC t HAC t SAC t DSC t C High Impedance CS R/C STS DB11– DB0 A O CE t SSR t SRR t HRR t HS t HD High-Z CS R/C STS DB11– DB0 t HSR A O t HAR t SAR Data Valid t HL t DD |
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Podobny opis - ADC574AKP |
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