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ADS7806UB Arkusz danych(PDF) 4 Page - Burr-Brown (TI) |
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ADS7806UB Arkusz danych(HTML) 4 Page - Burr-Brown (TI) |
4 / 18 page 4 ® ADS7806 DIGITAL PIN # NAME I/O DESCRIPTION TABLE I. Pin Assignments. ANALOG CONNECT R1IN CONNECT R2IN INPUT VIA 200 Ω VIA 100 Ω RANGE TO TO IMPEDANCE ±10V VIN CAP 45.7k Ω 0V to 5V AGND VIN 20.0k Ω 0V to 4V VIN VIN 21.4k Ω TABLE II. Input Range Connections. See also Figure 7. PIN CONFIGURATION V DIG V ANA REFD PWRD BUSY CS R/C BYTE TAG SDATA DATACLK D0 D1 D2 R1 IN AGND1 R2 IN CAP REF AGND2 SB/BTC EXT/INT D7 D6 D5 D4 D3 DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS7806 1R1IN Analog Input. See Figure 7. 2 AGND1 Analog Sense Ground. 3R2IN Analog Input. See Figure 7. 4 CAP Reference Buffer Output. 2.2 µF tantalum capacitor to ground. 5 REF Reference Input/Output. 2.2 µF tantalum capacitor to ground. 6 AGND2 Analog Ground. 7 SB/BTC I Selects Straight Binary or Binary Two’s Complement for Output Data Format. 8 EXT/INT I External/Internal data clock select. 9 D7 O Data Bit 3 if BYTE is HIGH. Data bit 11 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave unconnected when using serial output. 10 D6 O Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. 11 D5 O Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. 12 D4 O Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. 13 D3 O LOW if BYTE is HIGH. Data bit 7 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. 14 DGND Digital Ground. 15 D2 O LOW if BYTE is HIGH. Data bit 6 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. 16 D1 O LOW if BYTE is HIGH. Data bit 5 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. 17 D0 O LOW if BYTE is HIGH. Data bit 4 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. 18 DATACLK I/O Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH. 19 SDATA O Serial Output Synchronized to DATACLK. 20 TAG I Serial Input When Using an External Data Clock. 21 BYTE I Selects 8 most significant bits (LOW) or 4 least significant bits (HIGH) on parallel output pins. 22 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C enables the parallel output. 23 CS I Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same falling edge will start the transmission of serial data results from the previous conversion. 24 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs have been updated. 25 PWRD I PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active. 26 REFD I REFD HIGH shuts down the internal reference. External reference will be required for conversions. 27 VANA Analog Supply. Nominally +5V. Decouple with 0.1 µF ceramic and 10µF tantalum capacitors. 28 VDIG Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ V ANA. |
Podobny numer części - ADS7806UB |
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Podobny opis - ADS7806UB |
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