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ADS7852YB Arkusz danych(PDF) 9 Page - Burr-Brown (TI) |
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ADS7852YB Arkusz danych(HTML) 9 Page - Burr-Brown (TI) |
9 / 13 page 9 ® ADS7852 THEORY OF OPERATION The ADS7852 is a high-speed successive approximation register (SAR) analog-to-digital converter (A/D) with an internal 2.5V bandgap reference. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6mi- cron CMOS process. See Figure 1 for the basic operating circuit for the ADS7852. The ADS7852 requires an external clock to run the conver- sion process. This clock can vary between 200kHz (12.5Hz throughput) and 8MHz (500kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW times are at least 50ns and the clock period is at least 125ns. The minimum clock frequency is governed by the parasitic leakage of the Capacitive Digital-to-Analog (CDAC) capacitors internal to the ADS7852. The front-end input multiplexer of the ADS7852 features eight single-ended analog inputs. Channel selection is per- formed using the address pins A0 (pin 14), A1 (pin 13), and A2 (pin 12). When a conversion is initiated, the input voltage is sampled on the internal capacitor array. While a conversion is in progress, all channel inputs are discon- nected from any internal function (see Truth Table for addressing). The range of the analog input is set by the voltage on the VREF pin. With the internal 2.5V reference, the input range is 0V to 5V. An external reference voltage can be placed on VREF, overdriving the internal voltage. The range for the external voltage is 2.0V to 2.55V, giving an input voltage range of 4.0V to 5.1V. FIGURE 1. Typical Circuit Configuration. AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 ADS7852Y 10 µF + 0.1 µF +5V Analog Supply + 2.2 µF + 0.1 µF + 0V to 5V |
Podobny numer części - ADS7852YB |
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Podobny opis - ADS7852YB |
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