9

®

ADS820

THEORY OF OPERATION

The ADS820 is a high speed sampling analog-to-digital

converter with pipelining. It uses a fully differential archi-

tecture and digital error correction to guarantee 10-bit reso-

lution. The differential track/hold circuit is shown in Figure

1. The switches are controlled by an internal clock which has

a non-overlapping two phase signal,

φ1 and φ2. At the

sampling time the input signal is sampled on the bottom

plates of the input capacitors. In the next clock phase,

φ2, the

bottom plates of the input capacitors are connected together

and the feedback capacitors are switched to the op amp

is a held DC representation of the analog input at the sample

time. The track/hold circuit can also convert a single-ended

input signal into a fully differential signal for the quantizer.

The pipelined quantizer architecture has 9 stages with each

stage containing a two-bit quantizer and a two bit digital-to-

analog converter, as shown in Figure 2. Each two-bit quan-

tizer stage converts on the edge of the sub-clock, which is

twice the frequency of the externally applied clock. The

output of each quantizer is fed into its own delay line to

FIGURE 1. Input Track/Hold Configuration with Timing

Signals.

FIGURE 2. Pipeline A/D Architecture.

φ1

φ1

φ2

φ1

φ1

φ1

φ1

φ1

φ2

φ1

φ2

φ1

φ2

IN

IN

OUT

OUT

Op Amp

Bias

V

CM

Op Amp

Bias

V

CM

C

H

C

I

C

I

C

H

Input Clock (50%)

Internal Non-overlapping Clock

Σ

+

–

B1 (MSB)

B2

B3

B4

B5

B6

B7

B8

B9

B10 (LSB)

2-Bit

DAC

2-Bit

Flash

Input

T/H

Digital Delay

x2

x2

2-Bit

DAC

2-Bit

Flash

Digital Delay

2-Bit

Flash

Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

x2

IN

IN

STAGE 1

STAGE 2

STAGE 8

STAGE 9

Σ

+

–

Σ

+

–