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DAC2813 Arkusz danych(PDF) 4 Page - Burr-Brown (TI) |
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DAC2813 Arkusz danych(HTML) 4 Page - Burr-Brown (TI) |
4 / 9 page ® DAC2813 4 TIMING DIAGRAMS PIN NAME FUNCTION 1 DB11 DATA, MSB, positive true. 2 DB10 DATA 3 DB9 DATA 4 DB8 DATA 5 DB7 DATA 6 DB6 DATA 7 DB5 DATA 8 DB4 DATA 9 DB3 DATA 10 DB2 DATA 11 DB1 DATA 12 DB0 DATA, LSB. 13 RESET Resets output of all D/As to bipolar-zero. The D/A remains in this state until overwritten an LDAC-WR command. RESET does not reset the input latch. After power–up and reset, input latches will be in an indeterminant state. 14 WR Write strobe. Must be low for data transfer to any latch (except RESET). 15 EN2 Enable for 12-bit input data latch of D/A 2. NOTE: This logic path is slower than the WR\ path. 16 EN1 Enable for 12-bit input data latch of D/A 1. NOTE: This logic path is slower than the WR\ path. 17 LDAC Load DAC enable. Must be low with WR for data transfer to the D/A latch and simultaneous update of both D/A converters. 18 DCOM Digital common, logic currents return. 19 –VCC Analog supply input, nominally –12V or –15V referred to ACOM. 20 +VCC Analog supply input, nominally +12V or +15V referred to ACOM. 21 VREF OUT +10V reference output. 22 ACOM Analog common, +VCC, –VCC supply return. 23 BPO2 Bipolar offset. Connect to pin 21 (VREF OUT) through a 100Ω resistor or through a 200 potentiometer for Bipolar Offset Adjust for D/A 2. 24 BPO1 Bipolar offset. Connect to pin 21 (VREF OUT) through a 100Ω resistor or through a 200 potentiometer for Bipolar Offset Adjust or D/A 1. 25 VREF IN 2 Connect to VREF OUT through 500Ω fixed resistor or through a 1kΩ gain adjustment potentiometer for D/A 2. 26 VREF IN 1 Connect to VREF OUT through 500Ω fixed resistor or through a 1kΩ gain adjustment potentiometer for D/A 1. 27 VOUT 2 D/A 2 analog output. 28 VOUT 1 D/A 1 analog output. PIN DESCRIPTIONS TRUTH TABLE WR EN1 EN2 LDAC RESET OPERATION XXXX 0 Reset both D/A Latches. Does not reset input latches. 1 X X X 1 No Operation X 1 1 1 1 No Operation 0101 1 Load Data into First Rank for D/A 2 0011 1 Load Data into First Rank for D/A 1 0110 1 Load Second Rank from First Rank, both D/As 0000 1 All Latches Transparent “X” = Don’t Care > 5ns > 50ns > 50ns (Load first rank from Data Bus: LDAC = 1) DB11–DB0 WR > 50ns WRITE CYCLE #1 EN X ±1/2LSB Reset > 50ns +10V –10V 0V t SETTLING V OUT RESET COMMAND (Bipolar Mode) EN X, LDAC, WR = Don’t Care tSETTLING ±1/2LSB LDAC WR > 50ns > 50ns VOUT WRITE CYCLE #2 (Load second rank from first rank: EN X = 1) The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. |
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