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DAC3151IRGCT Arkusz danych(PDF) 8 Page - Texas Instruments |
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DAC3151IRGCT Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 56 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DACCLKP DACCLKN ALIGNP ALIGNN SYNCP SYNCN VFUSE (MSB) D11P D11N D10P D10N D9P D9N D8P D8N D1P TXENABLE ALARM SDO IOVDD SDIO SCLK SDENB RESETB NC NC NC NC D0N D0P (LSB) D1N GND PAD (backside) DAC3161 CLKVDD18 DAC3151 DAC3161 DAC3171 SLAS959A – AUGUST 2013 – REVISED AUGUST 2013 www.ti.com PINOUT – DAC3161 PIN ASSIGNMENT TABLE – DAC3161 PIN I/O DESCRIPTION NAME NO. CONTROL/SERIAL SCLK 43 I Serial interface clock. Internal pull-down. SDENB 42 I Serial interface clock. Internal pull-up. SDIO 44 I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register sif4_ena (config 0, bit 9)), the SDIO pin in an input only. Internal Pull-down. SDO 46 O Uni-directional serial interface data in 4 pin mode (register sif4_ena (config 0, bit 9)). The SDO pin is tri- stated in 3-pin interface mode (default). Internal Pulldown. RESETB 41 I Serial interface reset input. Active low. Initialized internal registers during high to low transition. Assynchronous. Internal pull-up. ALARM 47 O CMOS output for ALARM condition. TXENABLE 48 I Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal pull-down. SLEEP 49 I Puts device in sleep, active high. Internal pull-down. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DAC3151 DAC3161 DAC3171 |
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