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ADP3208AJCPZ-RL Arkusz danych(PDF) 9 Page - Analog Devices

Numer części ADP3208AJCPZ-RL
Szczegółowy opis  7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller
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ADP3208AJCPZ-RL Arkusz danych(HTML) 9 Page - Analog Devices

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ADP3208A
Rev. 2 | Page 9 of 38 | www.onsemi.com
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
EN
PWRGD
PGDELAY
CLKEN
FBRTN
FB
COMP
SS
ST
VARFREQ
VRTT
TTSNS
DRVH1
SW1
PVCC1
DRVL1
PGND1
PGND2
DRVL2
PVCC2
SW2
DRVH2
BST2
35
BST1
36
34
33
32
31
30
29
28
27
26
25
ADP3208
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 3. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
EN
Enable Input. Driving the pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT low,
and pulls CLKEN high.
2
PWRGD
Power Good Output. Open-drain output. A low logic state means that the output voltage is outside of the VID
DAC defined range.
3
PGDELAY
Power Good Delay Setting Input/Output. A capacitor connected from this pin to GND sets the power good delay
time.
4
CLKEN
Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to lock to the
external clock.
5
FBRTN
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the ground
return for the VID DAC and the voltage error amplifier blocks.
6
FB
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
7
COMP
Voltage Error Amplifier Output and Frequency Compensation Point.
8
SS
Soft Start and Latch-Off Delay Setting Input/Output. An external capacitor from this pin to GND sets the soft start
ramp-up time and the current limit latch-off delay ramp-down time.
9
ST
Soft Transient Slew Rate Timing Input/Output. A capacitor from this pin to GND sets the slew rate of the output
voltage when it transitions from one VID setting to another, including boot-to-active VID, VID on the fly, and
deeper sleep entry and exit transients.
10
VARFREQ
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.
11
VRTT
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator temperature
at the remote sensing point exceeded a set alarm threshold level.
12
TTSNS
Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected to
VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this pin and
acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling function and
disables the crowbar, or overvoltage protection (OVP), feature of the chip.
13
PMON
Power Monitor Output. Open-drain output. A pull-up resistor from PMON to CSREF provides a duty cycle
modulated power output signal. An external RC network can be used to convert the digital signal stream to an
averaged power analog output voltage.
14
PMONFS
Power Monitor Full-Scale Setting Input/Output. A resistor from this pin to GND sets the full-scale value of the
PMON output signal.
15
CLIM
Current Limit Setting Input/Output. An external resistor from this pin to GND sets the current limit threshold of
the converter.


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