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AD9051BRSZRL-2V Arkusz danych(PDF) 5 Page - Analog Devices |
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AD9051BRSZRL-2V Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 11 page REV. –5– AD9051 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1, 6, 7, 12, 21, 23 GND Ground 2, 8, 11 VD Analog 5 V Power Supply 3 VREFOUT Internal Bandgap Voltage Reference (Nominally 2.5 V) 4 VREFIN Input to Reference Amplifier. Voltage reference for ADC is connected here. 5 BWSEL Bandwidth Select. NC = 130 MHz nominal. +VD = 50 MHz nominal. 9 AINB Complementary Analog Input Pin (Analog Input Bar) 10 AIN Analog Input Pin 13 ENCODE Encode Clock Input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. 14 OR Out of Range Signal. Logic “0” when analog input is in nominal range. Logic “1” when analog input is out of nominal range. 15 D9 (MSB) Most Significant Bit of ADC Output 16–19 D8–D5 Digital Output Bits of ADC 20, 22 VDD Digital Output Power Supply (Only Used by Digital Outputs) 24–27 D4–D1 Digital Output Bits of ADC 28 D0 (LSB) Least Significant Bit of ADC Output PIN CONFIGURATION 14 13 12 11 10 9 8 1 2 3 4 7 6 5 17 16 20 28 27 26 25 24 23 22 21 19 18 15 TOP VIEW (Not to Scale) AD9051 GND D3 D2 D1 D0 (LSB) VD VREFOUT VREFIN VDD GND D4 BWSEL GND GND VD AINB AIN D5 VDD GND VD GND ENCODE OR D6 D9 (MSB) D8 D7 N N + 1 N + 2 N + 3 N + 4 N + 5 AIN ENCODE DIGITAL OUTPUTS tA tEH tEL tPD N – 5 N – 4 N – 3 N – 2 N – 1 N Figure 1. Timing Diagram 12k 12k 12k 12k AINB (PIN 9) AIN (PIN 10) INPUT BUFFER VD VDD (PINS 20, 22) +3V TO +5V D0–D9, OR VD ENCODE (PIN 13) VD VREFOUT (PIN 3) Figure 2. Equivalent Circuits Analog Input Encode Output Stage VREF C |
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