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UC3843AP-S08-R Arkusz danych(PDF) 7 Page - Unisonic Technologies |
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UC3843AP-S08-R Arkusz danych(HTML) 7 Page - Unisonic Technologies |
7 / 9 page UC3842A/3843A LINEAR INTEGRATED CIRCUIT UNISONICTECHNOLOGIESCO.,LTD 7 of 9 www.unisonic.com.tw QW-R103-002.G SHUTDOWN TECHNIQUES 8 3 1kΩ 1 Shutdown To current Sense resistor Shutdown Shutdown UTC UC3842A can be accomplished by two methods; either raise Pin 3 above 1V or pull Pin 1 below a voltage two diode drops above ground. Either method caused the output of PWM comparator to be high(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at Pins 1 and/or 3 is removed. In one example, an externally latched shut-down may be accomplished by adding an SCR which be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off allowing the SCR to reset. |
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