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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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CS4205 Arkusz danych(PDF) 36 Page - Cirrus Logic |
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CS4205 Arkusz danych(HTML) 36 Page - Cirrus Logic |
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36 / 80 page  CS4205 36 DS489PP2 5.15 Extended Audio ID Register (Index 28h) ID[1:0] Codec Configuration ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the CS4205 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4205 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 27 on page 63. AMAP Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode Control Register (Index 5Eh). The PCM playback and capture slots are mapped ac- cording to Table 14 on page 42. VRM Variable Rate Mic Audio. The VRM bit indicates whether variable rate Mic audio is supported. This bit always returns ‘1’, indicating that variable rate mic audio is available. VRA Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is support- ed. This bit always returns ‘1’, indicating that variable rate PCM audio is available. Default x209h. The Extended Audio ID Register (Index 28h) is a read-only register. 5.16 Extended Audio Status/Control Register (Index 2Ah) PRL Mic ADC Powerdown. When ‘set’, the PRL bit powers down the dedicated Mic ADC and cor- responding input gain stage. To use the dedicated Mic ADC, clear the PRL bit first. MADC Mic ADC Ready Status. When ‘set’, the MADC bit indicates the dedicated Mic ADC is ready to transmit data. VRM Enable Variable Rate Mic Audio. When ‘set’, the VRM bit allows access to the Mic ADC Rate Register (Index 34h). This bit must be ‘set’ in order to use variable mic capture rates. The VRM bit also serves as a powerdown for the Mic ADC SRC block. Clearing VRM will reset the Mic ADC Rate Register (Index 34h) to its default value and the SRC data path is flushed. VRA Enable Variable Rate Audio. When ‘set’, the VRA bit allows access to the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). This bit must be ‘set’ in order to use variable PCM playback or capture rates. The VRA bit also serves as a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at ‘0’. Default 4000h D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ID1 ID0 0 0 0 0 AMAP 00 00 0 VRM 00 VRA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 PRL 0 0 0 0 MADC 0 0 0 0 0 VRM 0 0 VRA |
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