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CS4220-KS Arkusz danych(PDF) 8 Page - Cirrus Logic |
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CS4220-KS Arkusz danych(HTML) 8 Page - Cirrus Logic |
8 / 32 page CS4220 CS4221 8 DS284PP3 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221) (TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF) Notes: 11. Not tested but guaranteed by design. 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 13. Data must be held for sufficient time to bridge the transition time of CCLK. 14. For FSCK < 1 MHz. Parameter Symbol Min Max Unit SPI Mode (SPI/I2C = 0) CCLK Clock Frequency fsck -6 MHz RST rising edge to CS falling (Note 11) tsrs 41 - µs CCLK edge to CS falling (Note 12) tspi 500 - ns CS High Time between transmissions tcsh 1.0 - µs CS falling to CCLK edge tcss 20 - ns CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK rising setup time tdsu 40 - ns CCLK rising to DATA hold time (Note 13) tdh 15 - ns Rise time of CCLK and CDIN (Note 14) tr2 -100 ns Fall time of CCLK and CDIN (Note 14) tf2 -100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN tcss t csh t spi t srs RST Figure 2. SPI Control Port Timing |
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