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CDB4226 Arkusz danych(PDF) 10 Page - Cirrus Logic |
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CDB4226 Arkusz danych(HTML) 10 Page - Cirrus Logic |
10 / 60 page CS4226 10 DS188F1 FUNCTIONAL DESCRIPTION Overview The CS4226 has 2 channels of 20-bit analog-to- digital conversion and 6 channels of 20-bit digital- to-analog conversion. A mono 20-bit ADC is also provided. All ADCs and DACs are delta-sigma converters. The stereo ADC inputs have adjustable input gain, while the DAC outputs have adjustable output attenuation. The device also contains an S/PDIF receiver capable of receiving compressed AC-3/MPEG or uncompressed digital audio data. Digital audio data for the DACs and from the ADCs is communicated over separate serial ports. This allows concurrent writing to and reading from the device. The CS4226 functions are controlled via a serial microcontroller interface. Figure 1 shows the recommended connection diagram for the CS4226. Analog Inputs Line Level Inputs AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L and AINAUX are the line level input pins (See Fig- ure 1). These pins are internally biased to the CMOUT voltage. A 10 µF DC blocking capacitor placed in series with the input pins allows signals centered around 0 V to be input to the CS4226. Fig- ure 2 shows an optional dual op amp buffer which combines level shifting with a gain of 0.5 to atten- uate the standard line level of 2 Vrms to 1 Vrms. The CMOUT reference level is used to bias the op- amps to approximately one half the supply voltage. With this input circuit, the 10 µF DC blocking caps in Figure 1 may be omitted. Any remaining DC off- set will be removed by the internal high-pass fil- ters. Selection of stereo the input pair (AIN1L/R, AIN2L/R or AIN3L/R) for the 20-bit ADC’s is ac- complished by setting the AIS1/0 bits (ADC analog input mux control), which are accessible in the ADC Control Byte. On-chip anti-aliasing filters follow the input mux providing anti-aliasing for all input channels. The analog inputs may also be configured as differ- ential inputs. This is enabled by setting bits AIS1/0=3. In the differential configuration, the left channel inputs reside on pins 10 and 11, and the right channel inputs reside on pins 12 and 13 as de- scribed in Table 1 below. In differential mode, the full scale input level is 2 Vrms. The analog signal is input to the mono ADC via the AINAUX pin. Independent Muting of both the stereo ADC’s and the mono ADC is possible through the ADC Con- trol Byte with the MUTR, MUTL and MUTM bits. Single-ended Pin # Differential Inputs AIN3L Pin 10 AINL+ AIN3R Pin 9 unused AIN2L Pin 11 AINL- AIN2R Pin 12 AINR- AIN1L Pin 14 unused AIN1R Pin 13 AINR+ Table 1. Single-ended vs Differential Input Pin Assignments + - 100 pF 10 k 20 k + - 10 k 100 pF 5 k 20 k Line In Right Line In Left CMOUT AINxR AINxL 0.47 µF 3.3 µF 3.3 µF Example Op-Amps are MC34074 or MC33078 Figure 2. Optional Line Input Buffer |
Podobny numer części - CDB4226 |
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Podobny opis - CDB4226 |
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