CS4228

DS307PP1

7

Notes: 8. After powering up the CS4228, RST should be held low until the power supplies and clocks are settled.

Parameter

Symbol

Typ

Max

Units

RST Low Time

(Note 8)

1-

-

ms

SCLK Falling Edge to SDOUT Output Valid

(DSCK=0)

-TBD

ns

LRCK Edge to MSB Valid

-TBD

ns

SDIN Setup Time Before SCLK Rising Edge

-TBD

ns

SDIN Hold Time After SCLK Rising Edge

-TBD

ns

Master Mode

SCLK Falling to LRCK Edge

+10

-

ns

SCLK Duty Cycle

50

-

%

Slave Mode

SCLK Period

--

ns

SCLK High Time

TBD

-

-

ns

SCLK Low Time

TBD

-

-

ns

SCLK rising to LRCK Edge

(DSCK=0)

TBD

-

-

ns

LRCK Edge to SCLK Rising

(DSCK=0)

TBD

-

-

ns

Figure 1. Serial Audio Port Master Mode Timing

SCLK*

(output)

LRCK

(output)

SDOUT

sckh

sckl

sckw

t

t

t

MSB

MSB-1

*SCLK shown for DSCK = 0.

SCLK inverted for DSCK = 1.

tdpd

SDOUT

LRCK

(input)

SCLK*

(input)

SDIN1

SDIN2

SDIN3

dh

t

ds

t

lrpd

t

lrcks

t

lrckd

t

Figure 2. Serial Audio Port Slave Mode Timing