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CS4297-JQ Arkusz danych(PDF) 7 Page - Cirrus Logic |
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CS4297-JQ Arkusz danych(HTML) 7 Page - Cirrus Logic |
7 / 46 page DS242F5 7 CS4297 CrystalClear™ SoundFusion™ Audio Codec ’97 DIGITAL CHARACTERISTICS (AVss = DVss = 0 V (See Grounding and Layout section)) SERIAL PORT TIMING Parameter Symbol Min Typ Max Unit Low level input voltage Vil - - 0.16 x DVdd V High level input voltage Vih 0.40 x DVdd - - V High level output voltage Voh 0.70 x DVdd 0.99 x DVdd - V Low level output voltage Vol - 0.03 0.10 x DVdd V Input Leakage Current (AC-link inputs) -10 - 10 µA Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA Output buffer drive current (Note 4) - 100 400 µA Parameter Symbol Min Typ Max Unit RESET Timing DVdd 90% maximum value to RESET# inactive pre-delay (Note 4) TVdd2rst# 1.5 - - ms RESET# active low pulse width Trst_low 1.0 - - µs RESET# inactive to BIT_CLK start-up delay Trst2clk - 42.7 - ms 1st SYNC active to CODEC READY set Tsync2crd - 40.6 - µs Clocks BIT_CLK frequency - 12.288 - MHz BIT_CLK period Tclk_period - 81.4 - ns BIT_CLK output jitter (depends on XTAL_IN source) - - 750 ps BIT_CLK high pulse width Tclk_high - 40.7 - ns BIT_CLK low pulse width Tclk_low - 40.7 - ns SYNC frequency - 48 - kHz SYNC period Tsync_period - 20.8 - µs SYNC high pulse width Tsync_high -1.3 - µs SYNC low pulse width Tsync_low - 19.5 - µs SYNC active to RESET# inactive pre-delay Trst2snyc - - 250 ms Data Setup and Hold Output Propagation delay from rising edge of BIT_CLK Tprop -6 8 ns Output hold from falling edge of BIT_CLK Tohold 5- - ns Input setup time from falling edge of BIT_CLK Tisetup 10 - - ns Input hold time from falling edge of BIT_CLK Tihold 0- - ns Input Signal rise time Tirise 2- 6 ns Input Signal fall time Tifall 2- 6 ns Output Signal rise time (Note 4) Tofall 24 6 ns Output Signal fall time (Note 4) Tofall 24 6 ns |
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