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CS43L41-KZ Arkusz danych(PDF) 10 Page - Cirrus Logic |
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CS43L41-KZ Arkusz danych(HTML) 10 Page - Cirrus Logic |
10 / 36 page CS43L41 10 DS473PP1 SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF) Notes: 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Parameter Symbol Min Max Unit I2C® Compatible Mode SCL Clock Frequency fscl -100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 11) thdd 0- µs SDA Setup time to SCL Rising tsud 250 - ns Rise Time of Both SDA and SCL Lines tr -1 µs Fall Time of Both SDA and SCL Lines tf -300 ns Setup Time for Stop Condition tsusp 4.7 - µs t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp Stop Start Start Stop Repeated SDA SCL t irs RST Figure 4. I2C Control Port Timing |
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