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FIN1532MTC Arkusz danych(PDF) 3 Page - Fairchild Semiconductor |
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FIN1532MTC Arkusz danych(HTML) 3 Page - Fairchild Semiconductor |
3 / 6 page 3 www.fairchildsemi.com AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Note 3: All typical values are at TA = 25°C and with VCC = 5V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc- tion. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V. All channels switching in phase. Note A: All input pulses have frequency = 10 MHz, t R or tF = 1 ns Note B: CL includes all probe and jig capacitances FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay Symbol Parameter Test Conditions Min Typ Max Units (Note 3) tPLH Propagation Delay 1.0 2.0 3.0 ns LOW-to-HIGH tPHL Propagation Delay 1.0 2.0 3.0 ns HIGH-to-LOW |VID| = 400 mV, CL = 10 pF, RL = 1kΩ tTLH Output Rise Time (20% to 80%) See Figure 1 and Figure 2 1.3 ns tTHL Output Fall Time (80% to 20%) 1.1 ns tSK(P) Pulse Skew |tPLH - tPHL| 0.2 0.5 ns tSK(LH), Channel-to-Channel Skew 0.1 0.3 ns tSK(HL) (Note 4) tSK(PP) Part-to-Part Skew (Note 5) 1.0 ns fMAX Maximum Operating Frequency RL = 1kΩ, CL = 10 pF, 200 260 MHz (Note 6) See Figure 1 and Figure 2 tZH LVTTL Output Enable Time from Z to HIGH RL = 1kΩ, CL = 10 pF, 8 12.0 ns tZL LVTTL Output Enable Time from Z to LOW See Figure 3 and Figure 4 8 12.0 ns tHZ LVTTL Output Disable Time from HIGH to Z 4 8.0 ns tLZ LVTTL Output Disable Time from LOW to Z 4 8.0 ns |
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Podobny opis - FIN1532MTC |
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