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AD9625BBPZ-2.0 Arkusz danych(PDF) 7 Page - Analog Devices

Numer części AD9625BBPZ-2.0
Szczegółowy opis  12-Bit, 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9625BBPZ-2.0 Arkusz danych(HTML) 7 Page - Analog Devices

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Data Sheet
AD9625
Timing Diagrams
Figure 2. SYSREF± Setup and Hold Timing
Figure 3. Serial Port Interface Timing Diagram (MSB First)
Figure 4. CLK Input and DOUT Timing Relationship (Generic Eight-Lane Mode)
CLK+
CLK–
SYSREF+
SYSREF–
tSU_SR
tH_SR
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
SDIO
SCLK
CSB
tS
tDS
tDH
tHIGH
tLOW
tCLK
tH
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
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JESD204B INTERFACE
M = 1; L = 8; N = 12; N' = 16; CF = 0; CS = 0; CS = 0...4; K = 32; HD = 1; F = 1
500ps MIN (2.0GHz)
CLK+
(ENCODE CLOCK)
LANE A±
@ 5.0Gbps
LANE B±
@ 5.0Gbps
LANE C±
@ 5.0Gbps
LANE D±
@ 5.0Gbps
LANE E±
@ 5.0Gbps
LANE F±
@ 5.0Gbps
LANE G±
@ 5.0Gbps
LANE H±
@ 5.0Gbps
SAMPLE N + 3 [3:0],
CCCC
SAMPLE N + 7 [3:0],
CCCC
SAMPLE N + 11 [3:0],
CCCC
SAMPLE N + 15 [3:0],
CCCC
SAMPLE N + 2 [3:0],
CCCC
SAMPLE N + 6 [3:0],
CCCC
SAMPLE N + 10 [3:0],
CCCC
SAMPLE N + 14 [3:0],
CCCC
SAMPLE N + 1 [3:0],
CCCC
SAMPLE N + 5 [3:0],
CCCC
SAMPLE N + 9 [3:0],
CCCC
SAMPLE N + 13 [3:0],
CCCC
SAMPLE N [3:0],
CCCC
SAMPLE N + 4 [3:0],
CCCC
SAMPLE N + 8 [3:0],
CCCC
SAMPLE N + 12 [3:0],
CCCC
SAMPLE N + 3 [11:4]
SAMPLE N + 7 [11:4]
SAMPLE N + 11 [11:4]
SAMPLE N + 15 [11:4]
SAMPLE N + 2 [11:4]
SAMPLE N + 6 [11:4]
SAMPLE N + 10 [11:4]
SAMPLE N + 14 [11:4]
SAMPLE N + 1 [11:4]
SAMPLE N + 5 [11:4]
SAMPLE N + 9 [11:4]
SAMPLE N + 13 [11:4]
SAMPLE N [11:4]
SAMPLE N + 4 [11:4]
SAMPLE N + 8 [11:4]
SAMPLE N + 12 [11:4]
F = 1 OCTETS
F = 1 OCTETS
F = 1 OCTETS
F = 1 OCTETS
Rev. 0 | Page 7 of 56


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