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SI537X-EVB Arkusz danych(PDF) 3 Page - Silicon Laboratories |
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SI537X-EVB Arkusz danych(HTML) 3 Page - Silicon Laboratories |
3 / 41 page Si321xPPQx-EVB Rev. 1.2 3 1.3. ProSLIC Evaluation Board Setup To prepare the ProSLIC evaluation board for use, perform the following steps: 1. Set power supplies to 3.3 V, 5 V, and 12 V. 2. With these supplies off, connect them to J3 and J4 corresponding to the silk screen designators. 3. Connect the PC’s parallel port (LPT1) to P1 (or J1) using a 25-pin D male-to-male cable. 4. Select the on-board PCM clock source, or select an external PCM source, and connect an Audio Precision SIA-2322 to P2 and P3 or a Wandel and Goltermann PCM-4 to J8, J9, J10, and J11. 5. TIP/RING connection can be made from the RJ-11 to a phone or telephony test equipment. 6. Invoke the ProSLIC LINC software. 7. Turn the power supplies on and press the ProSLIC evaluation board reset button (S1). 8. Click the “Reinitialize” button in the ProSLIC LINC software panel The ProSLIC is now ready to perform its linecard function. Table 2. Motherboard Power Connections J2, J3, J4 Si321x Si321xM VBRING NC NC VBHI NC NC VBLO NC NC GND GND GND1 GND1 GND +3 V +3.3 V2 +3.3 V2 +5 V +5 V +5 V +VIN +9 to 12 V3 +5 V3 Notes: 1. All three GND connection points are electrically connected on the board. 2. +3.3 V is only necessary if that is the desired VDD for operation. Si321x chooses +3.3 V or +5 V based on the SP1 of the motherboard (see schematic). 3. This may be changed based on application-specific circuits. Consult the dc-dc converter spreadsheet for other possible values. Table 3. On-Board PCLK Settings (S2) S2-1,2,3 S2-4 S2-5 S2-6 S2-7 S2-8 PCLK frequency Unused Unused Unused Unused FS enable 0,0,0 = 8.192 MHz 0,0,1 = 4.096 MHz 0,1,0 = 2.048 MHz 0,1,1 = 1.024 MHz 1,x,x = 512 kHz x x x x 0 = FS disabled 1 = FS enabled Note: 1 = on. Table 4. JP1–4 Settings Jumper Function Jumper Location Default Factory Setting 1–2 2–3 JP1 VDD Level Select +3 V +5 V 1–2 JP2 VPCM Level Select +3 V +5 V 2–3 JP3 FSYNC Level Select Internal External 1–2 JP4 PCLK Source Select Internal External 1–2 |
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