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SI7005EVB-UDP Arkusz danych(PDF) 4 Page - Silicon Laboratories |
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SI7005EVB-UDP Arkusz danych(HTML) 4 Page - Silicon Laboratories |
4 / 41 page Si7005 4 Rev. 1.2 1. Electrical Specifications Unless otherwise specified, all min/max specifications apply over the recommended operating conditions. Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Power Supply VDD 2.1 3.3 3.6 V Operating Temperature TA G grade –40 — 85 °C Operating Temperature TA F grade 0 — 70 °C Table 2. General Specifications 2.1 V DD 3.6 V; TA = 0 to 70 °C (F grade) or –40 to 85 °C (G grade) unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Unit Input Voltage High VIH CS, SCL, SDA pins 0.7xVDD —— V Input Voltage Low VIL CS, SCL, SDA pins — — 0.3xVDD V Input Voltage Range VIN SCL, SDA pins with respect to GND 0.0 — 3.6 V CS, CEXT pin with respect to GND 0.0 — VDD V Input Leakage IIL CS, SCL, SDA pins — — ±1 µA Output Voltage Low VOL SDA pin; IOL = 8.5 mA; VDD = 3.3 V —— 0.6 V SDA pin; IOL = 3.5 mA; VDD = 2.1 V —— 0.4 V Notes: 1. Si7005 can draw excess current if VDD and CS are ramped high together. To enter the lowest power mode, either hold CS low while VDD ramps or pulse CS low after VDD reaches its final value. 2. SDA and SCL pins have an internal 75 k pull-up resistor to VDD |
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