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ES1010SI Arkusz danych(PDF) 2 Page - Altera Corporation |
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ES1010SI Arkusz danych(HTML) 2 Page - Altera Corporation |
2 / 11 page Page 2 ES1010SI 12V Hot-Swap Power Distribution Controllers March 2014 Altera Corporation Ordering Information Pin Configuration ES1010SI (8 LD SOIC) TOP VIEW PART NUMBER (Notes 1, 3) PART MARKING TEMPERATURE RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ES1010SI 1010 -40 to +85 8 Ld SOIC M8.15 EVB-ES1010SI Evaluation Platform NOTES: 1. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.. Pin Descriptions PIN NO. SYMBOL FUNCTION DESCRIPTION 1 ISET- Current Set Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. 2 ISEN+ Current Sense Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. 3 GATE External FET Gate Drive Pin Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VIN +6.5V by an 14µA current source. 4 GND Chip Return 5 VIN Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated GND +12V supply. 6 CLTIM Current Limit Timing Capacitor Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93k x CLTIM. 7 POK Power Good Indicator Indicates that the voltage on the ISEN+ pin is satisfactory. POK is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN+) is less than the UV level for the particular IC. 8 EN Power-ON EN is used to control and reset the chip. The chip is enabled when EN pin is driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a current limit time-out, the chip is reset by a low level signal applied to this pin. This input has 20µA pull-up capability. ISET- ISEN+ GATE GND 1 2 3 4 8 7 6 5 EN POK CLTIM VIN 09617 March 14, 2014 Rev A |
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