© 2003 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

6

Required Specifications and Test Diagrams

Notes:

7.

Electrostatic Discharge Capability: Human Body Model and Machine Model ESD should be measured using MIL-

STD-883C method 3015.7 standard.

8.

Latch-up immunity should be tested to the EIA/JEDEC Standard Number 78 (EIA/JESD78).

Figure 3. Differential Receiver Voltage Definitions Test Circuit

Note:

9.

Table 1.

Receiver Minimum and Maximum Input Threshold Test Voltages

Applied Voltages (V)

Resulting Differential

Input Voltage (mV)

Resulting Common

Mode Input Voltage (V)

1.25

1.15

100

1.2

1.15

1.25

-100

1.2

100

-100

0.1

0.0

100

0.05

0.0

0.1

-100

0.05

1.75

0.65

1100

1.2

0.65

1.75

-1100

1.2

1100

-1100

1.1

0.0

1100

0.55

0.0

1.1

-1100

0.55

Figure 4. LVDS Output Circuit for DC Test

Note: