AD2S1210-EP

Rev. 0 | Page 4 of 16

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Settling Time 10° Step Input

10-bit

0.6

0.9

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

12-bit

2.2

3.3

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

14-bit

6.5

9.8

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

16-bit

27.5

48

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

Settling Time 179° Step Input

10-bit

1.5

2.4

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

12-bit

4.75

6.1

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

14-bit

10.5

15.2

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

16-bit

45

68

ms

To settle to within ±2 LSB, CLKIN = 8.192 MHz

EXC, EXC OUTPUTS

Voltage

3.2

3.6

4.0

V p-p

Load ±100 µA, typical differential output

(EXC to EXC) = 7.2 V p-p

Center Voltage

2.40

2.47

2.53

V

Frequency

2

20

kHz

EXC/EXC DC Mismatch

30

mV

EXC/EXC AC Mismatch

132

mV

THD

−58

dB

First five harmonics

VOLTAGE REFERENCE

REFOUT

2.40

2.47

2.53

V

Drift

100

ppm/°C

PSRR

−60

dB

CLKIN, XTALOUT6

0.8

V

2.0

V

LOGIC INPUTS

0.8

V

0.7

V

2.0

V

1.7

V

Pull-Up)

10

µA

80

µA

RES0, RES1, RD,

−10

µA

LOGIC OUTPUTS

0.4

V

2.4

V

2.0

V

−10

µA

10

µA

POWER REQUIREMENTS

4.75

5.25

V

4.75

5.25

V

2.3

5.25

V

POWER SUPPLY

12

mA

35

mA

2

mA

clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply.