UC3842/UC3843/UC3844/UC3845

7

Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two

diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The

PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins

1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be

Figure 9. Slope Compensation

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for

spikes.

Temperature (

°C)

Figure 10. Temperature Drift (Vref)

Temperature (

°C)

Figure 11. Temperature Drift (Ist)

Temperature (

°C)

Figure 12. Temperature Drift (Icc)

UC3842/UC3843