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MC100EP08 Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC100EP08 Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 11 page © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 6 1 Publication Order Number: MC10EP08/D MC10EP08, MC100EP08 3.3V / 5V ECL 2-Input Differential XOR/XNOR Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V • Open Input Default State • Safety Clamp on Inputs • Q Output Will Default LOW with Inputs Open or at VEE • These are Pb−Free Devices A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package H = MC10 K = MC100 5J = MC10 2Y = MC100 D = Date Code SOIC−8 D SUFFIX CASE 751 MARKING DIAGRAMS* TSSOP−8 DT SUFFIX CASE 948R HP08 ALYWG G KP082 ALYWG G 1 8 1 8 1 8 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ORDERING INFORMATION 1 8 HEP08 ALYWG G 1 8 KEP08 ALYWG G 1 8 DFN8 MN SUFFIX CASE 506AA 5J DG G 1 4 2Y DG G 1 4 (Note: Microdot may be in either location) |
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