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Zakładka z wyszukiwarką danych komponentów |
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ADC141S625 Arkusz danych(PDF) 6 Page - Texas Instruments |
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ADC141S625 Arkusz danych(HTML) 6 Page - Texas Instruments |
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6 / 27 page  DOUT tf tr 0.9 x VIO 0.1 x VIO 1.6V TO OUTPUT PIN CL 25 pF IOH IOL 2 mA 2 mA 4 5 11 12 13 14 15 16 tACQ (Power-Down) tCONV (Power-Up) DB13 DB12 DB5 DB4 DB3 DB2 1 D` SCLK CS 2 3 17 18 0 0 0 1 DB1 DB0 2 tEN tDIS tCL tCH 0 tCS ADC141S625 SNAS434A – NOVEMBER 2007 – REVISED JANUARY 2009 www.ti.com ADC141S626 Timing Specifications (1) The following specifications apply for VA = VIO = VREF= +2.7V to 5.5V and fSCLK = 0.9 to 4.5 MHz, CL = 25 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units 3 6 ns (min) tCSS CS Setup Time prior to an SCLK rising edge 1/fSCLK - 3 1/fSCLK - 6 ns (max) tDH DOUT Hold Time after an SCLK falling edge 10 6 ns (min) tDA DOUT Access Time after an SCLK falling edge 28 40 ns (max) tDIS DOUT Disable Time after the rising edge of CS (2) 10 20 ns (max) tCS Minimum CS Pulse Width 5 20 ns (min) tEN DOUT Enable Time after the falling edge of CS 32 51 ns (max) tCH SCLK High Time 67 89 ns (min) tCL SCLK Low Time 67 89 ns (min) tr DOUT Rise Time 7 ns tf DOUT Fall Time 7 ns (1) Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). (2) tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit. Timing Diagrams Figure 1. ADC141S626 Single Conversion Timing Diagram Figure 2. Timing Test Circuit Figure 3. DOUT Rise and Fall Times 6 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Links: ADC141S625 |
Podobny numer części - ADC141S625 |
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Podobny opis - ADC141S625 |
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