ADS1231

SBAS414C – JULY 2009 – REVISED DECEMBER 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or visit the device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range, unless otherwise noted.

ADS1231

UNIT

AVDD to GND

–0.3 to +6

V

DVDD to GND

–0.3 to +6

V

100, momentary

mA

Input current

10, continuous

mA

Analog input voltage to GND

–0.3 to AVDD + 0.3

V

Digital input voltage to GND

–0.3 to DVDD + 0.3

V

Human body model (HBM)

±2000

V

JEDEC standard 22, test method A114-C.01, all pins

Charged device model (CDM)

±500

V

JEDEC standard 22, test method C101, all pins

Maximum junction temperature

+150

°C

Operating temperature range

–40 to +85

°C

Storage temperature range

–60 to +150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

CAUTION: ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

THERMAL INFORMATION

ADS1231

SOIC (D)

UNITS

16 PINS

Junction-to-ambient thermal resistance

79.5

Junction-to-case (top) thermal resistance

37.5

Junction-to-board thermal resistance

37.1

°C/W

Junction-to-top characterization parameter

5.6

Junction-to-board characterization parameter

36.7

Junction-to-case (bottom) thermal resistance

n/a

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

Submit Documentation Feedback

Copyright © 2009–2010, Texas Instruments Incorporated