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TSB14AA1A

TSB14AA1AI

TSB14AA1AT

SLLA222 – JUNE 2006

During packet reception, the data information is received on RDATA and strobe information is received on

RSTRB. The received data and strobe information is decoded to recover the received clock signal and the serial

data bits, which are resynchronized to the local system clock. The serial data bits are split into two parallel

streams and sent to the associated LLC. The PHY-Link interface has been made compliant to IEEE 1394a–2000

including timing and transfer of register 0 to the link-layer automatically after every 1394 bus reset.

The TSB14AA1A is a 3.3 V device that provides LVCMOS level outputs. The TSB14AA1A is an asynchronous

only device.

NOTE:

This product is for high-volume applications only. For a complete datasheet or more

information contact support@ti.com.

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