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ADS8321 Arkusz danych(PDF) 10 Page - Texas Instruments |
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ADS8321 Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 20 page ADS8321 10 SBAS123B www.ti.com FIGURE 7. Timing Diagrams and Test Circuits for the Parameters in Table I. DESCRIPTION ANALOG VALUE Full-Scale Range 2 • VREF Least Significant 2 • VREF/65536 Bit (LSB) BINARY CODE HEX CODE +Full Scale +VREF – 1 LSB 0111 1111 1111 1111 7FFF Midscale 0V 0000 0000 0000 0000 0000 Midscale – 1LSB 0V – 1 LSB 1111 1111 1111 1111 FFFF –Full Scale –VREF 1000 0000 0000 0000 8000 DIGITAL OUTPUT BINARY TWO’S COMPLEMENT TABLE II. Ideal Input Voltages and Output Codes. DATA FORMAT The output data from the ADS8321 is in Binary Two’s Complement format as shown in Table II. This table repre- sents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. POWER DISSIPATION The architecture of the converter, the semiconductor fabrica- tion process, and a careful design allow the ADS8321 to convert at up to a 100kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS8321 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS8321 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see Figure 6). Ideally, each conversion should occur as quickly as possible, preferably at a 2.4MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components) but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power down mode is entered. D OUT 1.4V Test Point 3k Ω 100pF C LOAD Load Circuit for t dDO, tr, and tf Voltage Waveforms for D OUT Rise and Fall Times, tr, tf Voltage Waveforms for D OUT Delay Times, tdDO Voltage Waveforms for t dis NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Load Circuit for t dis and ten t r D OUT V OH V OL t f D OUT Test Point t dis Waveform 2, ten V CC t dis Waveform 1 100pF C LOAD 3k Ω t dis CS/SHDN DOUT Waveform 1(1) DOUT Waveform 2(2) 90% 10% V IH t dDO D OUT DCLOCK V OH V OL V IL t hDO Voltage Waveforms for t en 5 B11 6 t en CS/SHDN DCLOCK V OL D OUT |
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