 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
ADS7864 Arkusz danych(PDF) 11 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
ADS7864 Arkusz danych(HTML) 11 Page - Texas Instruments |
|
|
11 / 28 page  www.ti.com APPLICATIONS INFORMATION INTRODUCTION REFERENCE ANALOG INPUT SAMPLE-AND-HOLD SECTION ADS7864 ADS7864 Single−Ended Input Common Voltage −V REF to +VREF peak−to−peak Differential Input Common Voltage V REF peak−to−peak V REF peak−to−peak ADS7864 SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 signal, is 5ns. The average delta of repeated aperture delay values is typically 50ps (also known as aperture jitter). These specifications reflect the ability of the ADS7864 to capture AC input signals accurately at The ADS7864 is a high speed, low power, dual 12-bit the exact same moment in time. analog-to-digital converter (ADC) that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains dual 2µs successive approxi- Under normal operation, the REFOUT pin (pin 2) mation ADCs, six differential sample-and-hold ampli- should be directly connected to the REFIN pin (pin 1) fiers, an internal +2.5V reference with REFIN and to provide an internal +2.5V reference to the REFOUT pins and a high speed parallel interface. ADS7864. The ADS7864 can operate, however, with There are six analog inputs that are grouped into an external reference in the range of 1.2V to 2.6V for three channels (A, B and C). Each A/D converter has a corresponding full-scale range of 2.4V to 5.2V. three inputs (A0/A1, B0/B1 and C0/C1) that can be The internal reference of the ADS7864 is sampled and converted simultaneously, thus pre- double-buffered. If the internal reference is used to serving the relative phase information of the signals drive an external load, a buffer is provided between on both analog inputs. Each pair of channels has a the reference and the load applied to pin 33 (the hold signal (HOLDA, HOLDB, HOLDC) to allow internal reference can typically source 2mA of cur- simultaneous sampling on all six channels. The part rent—load capacitance should not exceed 100pF). If accepts an analog input voltage in the range of –VREF an external reference is used, the second buffer to +VREF, centered around the internal +2.5V refer- provides isolation between the external reference and ence. The part will also accept bipolar input ranges the CDAC. This buffer is also used to recharge all of when a level shift circuit is used at the front end (see the capacitors of both CDACs during conversion. Figure 25). A conversion is initiated on the ADS7864 by bringing the HOLDX pin low for a minimum of 15ns. HOLDX The analog input is bipolar and fully differential. There low places both sample-and-hold amplifiers of the X are two general methods of driving the analog input channels in the hold state simultaneously and the of the ADS7864: single-ended or differential (see conversion process is started on both channels. The Figure 19 and Figure 20). When the input is BUSY output will then go low and remain low for the single-ended, the –IN input is held at the com- duration of the conversion cycle. The data can be mon-mode voltage. The +IN input swings around the read from the parallel output bus following the con- same common voltage and the peak-to-peak ampli- version by bringing both RD and CS low. tude is the (common-mode +VREF) and the Conversion time for the ADS7864 is 1.75µs when an (common-mode –VREF). The value of VREF determines 8MHz external clock is used. The corresponding the range over which the common-mode voltage may acquisition time is 0.25µs. To achieve maximum vary (see Figure 21). output rate (500kHz), the read function can be performed during at the start of the next conversion. NOTE: This mode of operation is described in more detail in the Timing and Control section of this data sheet. The sample-and-hold amplifiers on the ADS7864 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the sample-and-hold is greater than the Nyquist rate of the ADC (Nyquist equals one-half of the sampling rate) even when the ADC is operated at its maximum throughput rate of 500kHz. The typical small-signal bandwidth of the sample-and-hold amplifiers is 40MHz. Typical aperture delay time, or the time it takes for Figure 19. Methods of Driving the ADS7864 the ADS7864 to switch from the sample to the hold Single-Ended or Differential mode following the negative edge of the HOLDX 11 |
Podobny numer części - ADS7864_14 |
|
Podobny opis - ADS7864_14 |
|
|
Link URL |
| Polityka prywatności |
| ALLDATASHEET.PL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
