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ADS7279IPWRG4 Arkusz danych(PDF) 5 Page - Texas Instruments |
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ADS7279IPWRG4 Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 51 page ELECTRICAL CHARACTERISTICS ADS7279 ADS7280 www.ti.com ............................................................................................................................................................... SBAS436A – MAY 2008 – REVISED JUNE 2009 At TA = –40°C to +85°C, +VA = 2.7V to 3.6V, +VBD = 1.65V to 1.5x(+VA), VREF = 2.5V, fSAMPLE = 1MHz for 3V ≤ +VA ≤ 3.6V, and fSAMPLE = 900kHz for 3V < +VA ≤ 2.7V using external clock, unless otherwise noted. ADS7279, ADS7280 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT FSR Full-scale input voltage(1) +IN – (–IN) or (+INx – COM) 0 VREF V +IN, +IN0, +IN1 AGND – 0.2 +VA + 0.2 Absolute input voltage V –IN or COM AGND – 0.2 AGND + 0.2 Input capacitance 45 pF No ongoing conversion, Input leakage current 50 nA dc Input At dc 108 Input channel isolation, ADS7280 dB only VIN = ±1.25VPP at 50kHz 101 SYSTEM PERFORMANCE Resolution 14 Bits No missing codes 14 Bits Integral INL –1 ±0.4 1 LSB(2) linearity DNL Differential linearity –1 ±0.4 1 LSB(2) Offset EO –0.8 ±0.05 0.8 mV error(3) Offset error drift FSR = 2.5V ±0.1 ppm/°C EG Gain error –0.25 ±0.06 0.25 %FSR Gain error drift ±0.5 ppm/°C At dc 70 CMRR Common-mode rejection ratio dB VIN = 0.4VPP at 1MHz 50 Noise 33 µV RMS PSRR Power-supply rejection ratio At FFFFh output code(3) 78 dB SAMPLING DYNAMICS tCONV Conversion time 18 CCLK tSAMPLE1 Manual trigger 3 Acquisition time CCLK tSAMPLE2 Auto trigger 3 2.7V ≤ +VA < 3.0V 0.9 Throughput rate MHz 3.0V ≤ +VA < 3.64V 1 Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns (1) Ideal input span; does not include gain or offset error. (2) LSB means least significant bit. (3) Measured relative to an ideal full-scale input [(+IN) – (–IN)] of 2.5V when +VA = 3V. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS7279 ADS7280 |
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