ADS1252

8

SBAS127D

www.ti.com

FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1252.

DELTA-SIGMA MODULATOR

The ADS1252 operates from a nominal system clock fre-

quency of 16MHz which is fixed in relation to the system

clock frequency that is divided by 6 to derive the modulator

frequency; therefore, with a system clock frequency of 16MHz,

the modulator frequency is 2.667MHz. Furthermore, the

oversampling ratio of the modulator is fixed in relation to the

modulator frequency. The oversampling ratio of the modula-

tor is 64, and with the modulator frequency running at

2.667MHz, the data rate is 41.667kHz; thus, using a slower

system clock frequency will result in a lower data output rate,

as shown in Table I.

TABLE I. CLK Rate versus Data Output Rate.

CLK (MHz)

DATA OUTPUT RATE (Hz)

41 667

40 000

30 063

38 400

37 287

32 000

31 250

28 800

26 042

9.600000

25 000

19 200

16 000

15 625

12 800

9 600

8 000

6 400

4 800

0.921600

2 400

0.460800

1 200

0.384000

1 000

0.192000

500

0.038400

100

0.023040

60

0.019200

50

0.011520

30

0.009600

25

0.007680

20

0.006400

16.67

0.005760

15

0.004800

12.50

0.003840

10

NOTE: (1) Standard Clock Oscillator.

REFERENCE INPUT

Reference input takes an average current of 220

µA with a

16MHz system clock; this current will be proportional to the

system clock. A buffered reference is recommended for

ADS1252. The recommended reference circuit is shown in

Figure 2.

Reference voltages higher than 4.096V will increase the full-

scale range, whereas the absolute internal circuit noise of the

converter remains the same. This will decrease the noise in

terms of ppm of full scale, which increases the effective

resolution (see the typical characteristic curve,

RMS Noise vs

DIGITAL FILTER

computes the digital result based on the most recent outputs

from the delta-sigma modulator. At the most basic level, the

digital filter can be thought of as simply averaging the

modulator results in a weighted form and presenting this

average as the digital output. The digital output rate, or data

rate, scales directly with the system CLK frequency, this

allows the data output rate to be changed over a very wide

range (five orders of magnitude) by changing the system

CLK frequency. However, it is important to note that the

–3dB point of the filter is 0.216 times the data output rate, so

the data output rate must allow for sufficient margin to

prevent attenuation of the signal of interest.

As the conversion result is essentially an average, the

data-output rate determines the location of the resulting

notches in the digital filter (see Figure 3). Note that the first

notch is located at the data-output rate frequency, and

subsequent notches are located at integer multiples of the

data-output rate to allow for rejection of not only the funda-

mental frequency, but also harmonic frequencies. In this

manner, the data-output rate can be used to set specific

notch frequencies in the digital filter response.

0.10

µF

+5V

10k

Ω

10

µF

4

3

2

7

6

+

0.10

µF

0.1

µF

10

µF

+

0.1

µF

OPA350

0.1

µF

+5V

3

1

2

To V

REF

Pin 8 of

the ADS1252

REF3140