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ADS1224IPWRG4 Arkusz danych(PDF) 9 Page - Texas Instruments

Numer części ADS1224IPWRG4
Szczegółowy opis  24-Bit Analog-to-Digital Converter with 4-Channel Differential in put Multiplexxer
Download  33 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1224IPWRG4 Arkusz danych(HTML) 9 Page - Texas Instruments

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ADS1224
SBAS286C − JUNE 2003 − REVISED JANUARY 2009
www.ti.com
9
Analog Input Measurement without the Input Buffer
With the buffer disabled by setting the BUFEN pin low, the
ADS1224 measures the input signal using internal
capacitors that are continuously charged and discharged.
Figure 14 shows a simplified schematic of the ADS1224
input circuitry, with Figure 15 showing the on/off timings of
the switches. The S1 switches close during the input
sampling phase. With S1 closed, CA1 charges to AINP,
CA2 charges to AINN, and CB charges to (AINP – AINN).
For the discharge phase, S1 opens first and then S2
closes. CA1 and CA2 discharge to approximately AVDD/2
and
CB
discharges
to
0V.
This
two-phase
sample/discharge cycle repeats with a frequency of
fCLK/32 (62.5kHz for fCLK = 2MHz).
Mux
AVDD
AVDD/2
AVDD/2
S
1
S
1
AINN
AINP
S
2
C
A1
3pF
C
B
6pF
C
A2
3pF
AVDD
ESD Protection
AINPx
AINNx
S
2
Figure 14. Simplified Input Structure with the
Buffer Turned Off
ON
OFF
ON
S
1
S
2
OFF
t
SAMPLE = 32/fCLK
Figure 15. S1 and S2 Switch Timing for Figure 14
The constant charging of the input capacitors presents
a load on the inputs that can be represented by effective
impedances. Figure 16 shows the input circuitry with
the capacitors and switches of Figure 14 replaced by
their effective impedances. These impedances scale
inversely with fCLK frequency. For example, if fCLK
frequency is reduced by a factor of 2, the impedances
will double.
Zeff
A =tSAMPLE/CA1 =6MΩ
(1)
Zeff
B =tSAMPLE/CB =3MΩ
(1)
Zeff
A =tSAMPLE/CA2 =6MΩ
(1)
NOTE: (1) fCLK =2MHz.
AINPx
AINNx
AVDD/2
AVDD/2
Figure 16. Effective Analog Input Impedances
with the Buffer Off
ESD diodes protect the inputs. To keep these diodes
from turning on, make sure the voltages on the input
pins do not go below GND by more than 100mV, and
likewise do not exceed AVDD by 100mV:
GND – 100mV < (AINP, AINN) < AVDD + 100mV
Analog Input Measurement with the Input Buffer
When the buffer is enabled by setting the BUFEN pin
high, a low-drift, chopper-stabilized input buffer is used
to achieve very high input impedance. The buffer
charges the input sampling capacitors, thus removing
the load from the measurement. Because the input
buffer is chopper-stabilized, the charging of parasitic
capacitances causes the charge to be carried away, as
if by resistance. The input impedance can be modeled
by a single resistor, as shown in Figure 17. The
impedance scales inversely with fCLK frequency, as in
the nonbuffered case. Note that during standby mode,
the buffer must be disabled to prevent loading of the
inputs.
AINP
AINN
1.2G
(1)
NOTE: (1) f
CLK =2MHz.
Figure 17. Effective Analog Input Impedances
with the Buffer On
Note also that the analog inputs (listed in the Electrical
Characteristics table as Absolute Input Range) must
remain between GND + 0.05V to AVDD − 1.5V.
Exceeding this range degrades linearity and results in
performance outside the specified limits.


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