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ADS1120IPW Arkusz danych(PDF) 3 Page - Texas Instruments

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Numer części ADS1120IPW
Szczegółowy opis  Low-Power, Low-Noise, 16-Bit, Analog-to-Digital Converter for Small-Signal Sensors
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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ADS1120IPW Arkusz danych(HTML) 3 Page - Texas Instruments

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ADS1120
www.ti.com
SBAS535A – AUGUST 2013 – REVISED JANUARY 2014
Electrical Characteristics
Minimum and maximum specifications are at TA = –40°C to +125°C. Typical specifications are at TA = +25°C.
All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external VREF = 2.5 V,
unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale differential input voltage
VIN = (VAINP – VAINN)
±VREF / gain
(2)
V
range
PGA disabled, gain = 1 to 4
AVSS – 0.1
AVDD + 0.1
V
Absolute input voltage range
Gain = 1 to 128
See the Low-Noise PGA section
V
PGA disabled, gain = 1 to 4
AVSS – 0.1
AVDD + 0.1
V
Common-mode input voltage range
VCM
[VCM = (VAINP + VAINN) / 2]
Gain = 1 to 128
See the Low-Noise PGA section
Absolute input current
See the Typical Characteristics
Differential input current
See the Typical Characteristics
SYSTEM PERFORMANCE
Resolution (no missing codes)
16
Bits
Normal mode
20, 45, 90, 175, 330, 600, 1000
SPS
DR
Data rate
Duty-cycle mode
5, 11.25, 22.5, 44, 82.5, 150, 250
SPS
Turbo mode
40, 90, 180, 350, 660, 1200, 2000
SPS
Noise (input-referred)
See the Noise Performance section
Gain = 1 to 128, VCM = 0.5 AVDD,
INL
Integral nonlinearity
8
20
ppm
best fit(3)
PGA disabled, gain = 1 to 4, TA = +25°C,
±4
µV
differential inputs
VIO
Offset voltage (input-referred)
Gain = 1 to 128, TA = +25°C,
±4
µV
differential inputs
PGA disabled, gain = 1 to 4
0.25
µV/°C
Offset drift
Gain = 1 to 128, TA = –40°C to +85°C
(3)
0.08
0.3
µV/°C
Gain = 1 to 128
0.25
µV/°C
PGA disabled, gain = 1 to 4, TA = +25°C
±0.015%
GE
Gain error
Gain = 1 to 128, TA = +25°C
–0.1%
±0.015%
0.1%
PGA disabled, gain = 1 to 4
1
ppm/°C
Gain drift
Gain = 1 to 128(3)
1
4
ppm/°C
50 Hz ±3%, DR = 20 SPS, external CLK,
105
dB
50/60 bit = 10
60 Hz ±3%, DR = 20 SPS, external CLK,
NMRR
Normal-mode rejection ratio(3)
105
dB
50/60 bit = 11
50 Hz or 60 Hz ±3%, DR = 20 SPS,
90
dB
external CLK, 50/60 bit = 01
At dc and gain = 1
90
105
dB
CMRR
Common-mode rejection ratio
fCM = 50 Hz, DR = 2000 SPS
(3)
95
115
dB
fCM = 60 Hz, DR = 2000 SPS
(3)
95
115
dB
AVDD at dc, VCM = 0.5 AVDD, gain = 1
80
105
dB
PSRR
Power-supply rejection ratio
DVDD at dc, VCM = 0.5 AVDD, gain = 1
(3)
100
115
dB
INTERNAL VOLTAGE REFERENCE
Initial accuracy
TA = +25°C
2.045
2.048
2.051
V
Reference drift(3)
5
40
ppm/°C
Long-term drift
1000 hours
110
ppm
VOLTAGE REFERENCE INPUT
VREF
Reference input range
VREF = VREFPx – VREFNx
0.75
2.5
AVDD
V
Negative reference absolute input
REFNx to AVSS
AVSS – 0.1
VREFPx – 0.75
V
Positive reference absolute input
REFPx to AVSS
VREFNx + 0.75
AVDD + 0.1
V
Reference input current
REFN0 = AVSS, REFP0 = VREF
±10
nA
(1)
PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.
See the Bypassing the PGA section for more information.
(2)
Limited to [(AVDD – AVSS) – 0.4 V] / gain, when the PGA is enabled.
(3)
Minimum and maximum values are ensured by design and characterization data.
Copyright © 2013–2014, Texas Instruments Incorporated
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