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ADS8548 Arkusz danych(PDF) 11 Page - Texas Instruments |
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ADS8548 Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 52 page CONVST_x BUSY (C27=C26=0) CS DB[15:0] t DCVB t CONV t BUCS t CSCV t CVL RD t CSRD CH A0 CH A1 CH B0 CH B1 CH C0 CH C1 t RDCS t PDDO t RDL t HDO t RDH CH D0 CH D1 t DTRI t ACQ ADS8528 ADS8548 ADS8568 www.ti.com SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 Figure 2. Parallel Read Access Timing Diagram Table 2. Parallel Interface Timing Requirements (Read Access)(1)(2) ADS8528, ADS8548, ADS8568 TEST PARAMETER CONDITION MIN TYP MAX UNIT tCVL CONVST_x low time 20 ns tACQ Acquisition time 280 ns 19 20 tCCLK or tXCLK ADS8528, 1.33 µs CLKSEL = 0 tCONV Conversion time ADS8548, 1.45 µs CLKSEL = 0 ADS8568, 1.7 µs CLKSEL = 0 tDCVB CONVST_x high to BUSY high delay 25 ns tBUCS BUSY low to CS low time 0 ns ADS8528 0 ns Bus access finished to next conversion tCSCV ADS8548 20 ns start time(3) ADS8568 40 ns tCSRD CS low to RD low time 0 ns tRDCS RD high to CS high time 0 ns tRDL RD pulse width 20 ns tRDH Minimum time between two read accesses 2 ns RD or CS falling edge to data valid propagation tPDDO 15 ns delay tHDO Output data to RD or CS rising edge hold time 5 ns tDTRI CS high to DB[15:0] three-state delay 10 ns (1) Over recommended operating free-air temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted. (2) All input signals are specified with tR = tF = 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2. (3) Refer to CS signal or RD, whichever occurs first. Copyright © 2011, Texas Instruments Incorporated 11 Product Folder Link(s): ADS8528 ADS8548 ADS8568 |
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