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ADS7851IRTET Arkusz danych(PDF) 8 Page - Texas Instruments |
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ADS7851IRTET Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 38 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCLK CS 0 0 ChA D11 ChA D10 ChA D9 ChA D8 ChA D7 ChA D6 ChA D5 ChA D4 SDO-A tSU_CSCK tDV_CSDO tD_CKDO tDZ_CSDO Sample N Sample N + 1 tACQ tCONV tTHROUGHPUT Data From Sample N ChA D3 ChA D2 ChA D1 ChA D0 tPH_CS tPH_CK tPL_CK tSCLK tD_CKCS 0 0 ChB D11 ChB D10 ChB D9 ChB D8 ChB D7 ChB D6 ChB D5 ChB D4 SDO-B ChB D3 ChB D2 ChB D1 ChB D0 ADS7251, ADS7851 SBAS587A – JANUARY 2014 – REVISED APRIL 2014 www.ti.com 6.8 ADS7251 Timing Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fTHROUGHPUT Throughput fCLK = max 2000 kSPS fCLK CLOCK frequency fTHROUGHPUT = max 32 MHz tCLK CLOCK period fTHROUGHPUT = max 31.25 ns tPH_CK CLOCK high time 0.45 0.55 tCLK tPL_CK CLOCK low time 0.45 0.55 tCLK tCONV Conversion time tSU_CSCK + 12 tCLK ns tACQ Acquisition time fCLK = max 75 ns tPH_CS CS high time 30 ns tD_CKDO SCLK rising edge to (next) data valid 15 ns tDV_CSDO CS falling to data enable 10 ns Delay time tD_CKCS Last SCLK rising to CS rising 5 ns tDZ_CSDO CS rising to DOUT going to 3-state 10 ns tSU_CSCK Setup time CS falling to SCLK falling 15 ns Figure 1 shows the details of the serial interface between the ADS7251 and the digital host controller. Figure 1. ADS7251 Serial Interface Timing Diagram 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS7251 ADS7851 |
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