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CD74HCT4066-Q1 Arkusz danych(PDF) 6 Page - Texas Instruments |
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CD74HCT4066-Q1 Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 17 page CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION Test Point From Output Under Test CL (see Note A) VCC S1 S2 LOAD CIRCUIT PARAMETER tPZH tpd tdis ten tPZL tPHZ tPLZ Open Closed S1 Closed Open S2 Open Closed Closed Open Open Open NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. RL = 1 kΩ VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 1.3 V 1.3 V 1.3 V 10% 90% 90% 3 V VOH VOL 0 V tr tf Input In-Phase Output 1.3 V tPLH tPHL 1.3 V 1.3 V 10% 90% 90% VOH VOL tr tf tPHL tPLH Out-of-Phase Output Output Control Output Waveform 1 (see Note B) Output Waveform 2 (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ ≈VCC 0 V 1.3 V 10% 1.3 V ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES 1.3 V 1.3 V 90% 3 V 10% 10% Figure 6. Load Circuit and Voltage Waveforms |
Podobny numer części - CD74HCT4066-Q1_14 |
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Podobny opis - CD74HCT4066-Q1_14 |
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