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ADC0820CCWM Arkusz danych(PDF) 5 Page - Texas Instruments |
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ADC0820CCWM Arkusz danych(HTML) 5 Page - Texas Instruments |
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5 / 29 page  ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 AC Electrical Characteristics The following specifications apply for VCC = 5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(−) = 0V and TA = 25°C unless otherwise specified. Tested Design Parameter Conditions Typ(1) Units Limit(2) Limit(3) tCRD, Conversion Time for RD Mode Pin 7 = 0 (Figure 4) 1.6 2.5 µs tACC0, Access Time (Delay from Falling Pin 7 = 0 (Figure 4) tCRD + 20 tCRD + 50 ns Edge of RD to Output Valid) tCWR-RD, Conversion Time for WR-RD Pin 7 = VCC; tWR = 600 ns, tRD=600 ns 1.52 µs Mode (Figure 5 & Figure 6) Min Pin 7 = VCC (Figure 5 & Figure 6) 600 ns tWR, Write Time Max Figure 11(4) 50 µs Pin 7 = VCC (Figure 5 & Figure 6 & tRD, Read Time Min 600 ns Figure 12)(4) Pin 7 = VCC, tRD < tI, CL = 15pF (Figure 5) 190 280 ns tACC1, Access Time (Delay from Falling Edge of RD to Output Valid) CL = 100 pF 210 320 ns Pin 7 = VCC, tRD > tI, CL = 15pF (Figure 6) 70 120 ns tACC2, Access Time (Delay from Falling Edge of RD to Output Valid) CL=100 pF 90 150 ns tACC3, Access Time (Delay from Rising RPULLUP = 1k and CL = 15 pF 30 ns Edge of RDY to Output Valid) Pin 7 = VCC, CL = 50pF (Figure 6 & tI, Internal Comparison Time 800 1300 ns Figure 7) t1H, t0H, TRI-STATE Control (Delay from RL = 1k, CL = 10 pF 100 200 ns Rising Edge of RD to Hi-Z State) Pin 7 = VCC, CL = 50 pF tRD > tI (Figure 6) tI ns tINTL, Delay from Rising Edge of WR to Falling Edge of INT tRD < tI (Figure 5) tRD+200 tRD+290 ns tINTH, Delay from Rising Edge of RD to CL = 50pF (Figure 4 & Figure 5 & Figure 6) 125 225 ns Rising Edge of INT tINTHWR, Delay from Rising Edge of WR to CL = 50pF (Figure 7) 175 270 ns Rising Edge of INT tRDY, Delay from CS to RDY CL = 50 pF, Pin 7 = 0 (Figure 4) 50 100 ns tID, Delay from INT to Output Valid See Figure 7 20 50 ns tRI, Delay from RD to INT Pin 7 = VCC, tRD<tI Figure 5 200 290 ns tP, Delay from End of Conversion to Next (Figure 4 & Figure 5 & Figure 6 & Figure 7 500 ns Conversion & Figure 13)(4) Slew Rate, Tracking 0.1 V/µs CVIN, Analog Input Capacitance 45 pF COUT, Logic Output Capacitance 5 pF CIN, Logic Input Capacitance 5 pF (1) Typicals are at 25°C and represent most likely parametric norm. (2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). (3) Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. (4) Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Figure 11 and Figure 12 graphs. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC0820-N |
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