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ADS62P22IRGCT Arkusz danych(PDF) 8 Page - Texas Instruments |
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ADS62P22IRGCT Arkusz danych(HTML) 8 Page - Texas Instruments |
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8 / 78 page  ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are specified at 25 °C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), I O = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. ADS62P25 ADS62P24 ADS62P23 ADS62P22 FS = 125 MSPS FS = 105 MSPS FS = 80 MSPS FS = 65 MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Aperture ta 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns delay Aperture channel-to-channel delay within a device ±80 ±80 ±80 ±80 ps variation Aperture tj 150 150 150 150 fs rms jitter from global 15 50 15 50 15 50 15 50 μs powerdown Wake-up time from standby 15 50 15 50 15 50 15 50 μs (to valid from output CMOS 100 200 100 200 100 200 100 200 ns data) buffer LVDS 200 500 200 500 200 500 200 500 ns disable Default, after reset clock 14 14 14 14 cycles with low latency clock Latency 10 10 10 10 mode enabled cycles with digital filter clock 15 15 15 15 enabled cycles DDR LVDS MODE(4), DRVDD = 3.0 V to 3.6V Data valid (6) to Data setup tsu zero-cross of 0.6 1.5 1.0 2.3 2.4 3.8 3.8 5.2 ns time(5) CLKOUTP Zero-cross of Data hold th CLKOUTP to data 1.0 2.3 1.0 2.3 1.0 2.3 1.0 2.3 ns time(5) becoming invalid(6) Input clock rising Clock edge zero-cross to tPDI propagation 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 ns output clock rising delay edge zero-cross Duty cycle of differential clock, LVDS bit (CLKOUTP- clock duty 46% 50% 53% 46% 50% 53% 46% 50% 53% 46% 50% 53% CLKOUTM) cycle 10 ≤ Fs ≤ 125 MSPS Rise time measured from –50 mV to 50 Data rise mV tr time, Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps tf Data fall from 50 mV to –50 time mV 1 ≤ Fs ≤ 125 MSPS Rise time measured Output from –50 mV to 50 clock rise mV tCLKRISE time, Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps tCLKFALL Output from 50 mV to –50 clock fall mV time 1 ≤ Fs ≤ 125 MSPS (1) Timing parameters are specified by design and characterization and not tested in production. (2) CL is the effective external single-ended load capacitance between each output pin and ground. (3) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. (4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. (5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to logic high of +100 mV and logic low of –100 mV. 8 Copyright © 2007–2011, Texas Instruments Incorporated |
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