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ADS7886SBDCKR Arkusz danych(PDF) 5 Page - Texas Instruments |
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ADS7886SBDCKR Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 24 page ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 TIMING REQUIREMENTS (see Figure 1 and Figure 2) All specifications typical at TA = –40°C to 125°C, VDD = 2.35 V to 5.25 V (unless otherwise specified). PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT VDD = 3 V 16 × tSCLK tconv Conversion time ADS7866 ns VDD = 5 V 16 × tSCLK VDD = 3 V 40 Minimum quiet time needed from bus 3-state to start tq ns of next conversion VDD = 5 V 40 VDD = 3 V 15 25 td1 Delay time, CS low to first data (0) out ns VDD = 5 V 13 25 VDD = 3 V 10 tsu1 Setup time, CS low to SCLK low ns VDD = 5 V 10 VDD = 3 V 15 25 td2 Delay time, SCLK falling to SDO ns VDD = 5 V 13 25 VDD < 3 V 7 th1 Hold time, SCLK falling to data valid(2) ns VDD > 5 V 5.5 VDD = 3 V 10 25 td3 Delay time, 16th SCLK falling edge to SDO 3-state ns VDD = 5 V 8 20 VDD = 3 V 25 40 tw1 Pulse duration, CS ns VDD = 5 V 25 40 VDD = 3 V 17 30 td4 Delay time, CS high to SDO 3-state ns VDD = 5 V 15 25 VDD = 3 V 0.4 × tSCLK twH Pulse duration, SCLK high ns VDD = 5 V 0.4 × tSCLK VDD = 3 V 0.4 × tSCLK twL Pulse duration, SCLK low ns VDD = 5 V 0.4 × tSCLK VDD = 3 V 20 Frequency, SCLK MHz VDD = 5 V 20 Delay time, second falling edge of clock and CS to VDD = 3 V -2 5 td5 enter in powerdown (use min spec not to accidently ns VDD = 5 V -2 5 enter in powerdown) Figure 2 Delay time, CS and 10th falling edge of clock to VDD = 3 V 2 -5 td6 enter in powerdown (use max spec not to accidently ns VDD = 5 V 2 -5 enter in powerdown) Figure 2 (1) 3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V. (2) With 50-pf load. Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS7886 |
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