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ADS7868IDBVRG4 Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS7868IDBVRG4 Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 29 page www.ti.com TIMING REQUIREMENTS (1) (2) 1 2 3 5 4 6 10 16 14 12 1 9 SCLK SDO Hi−Z Auto Power− Down 7 8 Last SCLK= 16 for ADS 7866 14for ADS 7867 12for ADS 7868 Hi−Z Auto Power−Down 2 tSU(CSF−FSCLKF) tC(SCLK) tWH(SCLK) tWL(SCLK) tWH(CS) tSU(LSBZ−CSF) tDIS(EOC−SDOZ) tSU(CSF−FSCLKF) tD(CSF−SDOVALID) “0” “0” “0” tCONVERT “0” “0” “0” tH(SCLKF−SDOVALID) tD(SCLKF−SDOVALID) tD(CSF−SDOVALID) tSAMPLE “0” HOLD EOC CS tCYCLE MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB ADS7866 ADS7867 ADS7868 SLAS465 – JUNE 2005 At –40°C to 85°C, f SCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V, 50-pF Load on SDO Pin, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tsample Sample time tSU(CSF-FSCLKF) + 2 × tC(SCLK) µs ADS7866 13 × t C(SCLK) tconvert Conversion time ADS7867 11 × t C(SCLK) µs ADS7868 9 × t C(SCLK) 1.2 V ≤ V DD < 1.6 V See (3) 100 1.6 V ≤ V DD < 1.8 V See (3) 100 tC(SCLK) Cycle time µs 1.8 V ≤ V DD < 2.5 V See (3) 50 2.5 V ≤ V DD ≤ 3.6 V See (3) 6.7 tWH(SCLK) Pulse duration 0.4 × t C(SCLK) 0.6 × t C(SCLK) ns tWL(SCLK) Pulse duration 0.4 × t C(SCLK) 0.6 × t C(SCLK) ns 1.2 V ≤ V DD < 1.6 V 192 tSU(CSF-FSCLKF) Setup time 1.6 V ≤ V DD < 1.8 V 55 ns 1.8 V ≤ V DD ≤ 3.6 V 55 1.2 V ≤ V DD < 1.6 V 65 tD(CSF-SDOVALID) Delay time 1.6 V ≤ V DD < 1.8 V 55 ns 1.8 V ≤ V DD ≤ 3.6 V 55 1.2 V ≤ V DD < 1.6 V 20 tH(SCLKF-SDOVALID) Hold time 1.6 V ≤ V DD < 1.8 V 10 ns 1.8 V ≤ V DD ≤ 3.6 V 10 1.2 V ≤ V DD < 1.6 V 140 tD(SCLKF-SDOVALID) Delay time 1.6 V ≤ V DD < 1.8 V 140 ns 1.8 V ≤ V DD ≤ 3.6 V 140 1.2 V ≤ V DD < 1.6 V 10 80 tDIS(EOC-SDOZ) Disable time 1.6 V ≤ V DD < 1.8 V 7 60 ns 1.8 V ≤ V DD ≤ 3.6 V 7 60 1.2 V ≤ V DD < 1.6 V 20 tWH(CS) Pulse duration 1.6 V ≤ V DD < 1.8 V 10 ns 1.8 V ≤ V DD ≤ 3.6 V 10 1.2 V ≤ V DD < 1.6 V 20 tSU(LSBZ-CSF) Setup time 1.6 V ≤ V DD < 1.8 V 10 ns 1.8 V ≤ V DD ≤ 3.6 V 10 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram in Figure 1. (3) Min tC(SCLK) is determined by the Min tSAMPLE of the specific resolution and supply voltage. See Acquisition Time, Conversion Time, and Total Cycle Time section for further details. Figure 1. Timing Diagram 9 |
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Podobny opis - ADS7868IDBVRG4 |
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