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ADS1286UCG4 Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS1286UCG4 Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 18 page 9 ® ADS1286 CS/SHDN D OUT DCLOCK t DATA t SUCS t CSD t CYC t CONV POWER DOWN t SMPL Note: (1) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output LSB-First data then followed with zeroes indefinitely. B11 (MSB) B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1) NULL BIT HI-Z HI-Z B11 B10 B9 B8 NULL BIT CS/SHDN D OUT DCLOCK t CONV t DATA t SUCS t CYC POWER DOWN t SMPL Note: (2) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output zeroes indefinitely. t DATA: During this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes. B11 (MSB) B10 B9 B8 B7 B6 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 NULL BIT HI-Z HI-Z B5 B6 B7 B8 B9 B10 B11 (2) t CSD leaving the DCLOCK running to clock out the LSB first data or zeroes. If the CS input is not running rail-to-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CS pin to ground when it is low and to supply voltage when it is high. SERIAL INTERFACE The ADS1286 communicates with microprocessors and other external digital systems via a synchronous 3-wire serial inter- face. DCLOCK synchronizes the data transfer with each bit being transmitted on the falling DCLOCK edge and captured on the rising DCLOCK edge in the receiving system. A falling CS initiates data transfer as shown in Figure 1. After CS falls, the second DCLOCK pulse enables DOUT. After one null bit, the A/D conversion result is output on the DOUT line. Bringing CS high resets the ADS1286 for the next data exchange. MICROPOWER OPERATION With typical operating currents of 250 µA and automatic shutdown between conversions, the ADS1286 achieves ex- tremely low power consumption over a wide range of sample rates (see Figure 2). The auto-shutdown allows the supply current to drop with sample rate. SHUTDOWN The ADS1286 is equipped with automatic shutdown fea- tures. The device draws power when the CS pin is LOW and shuts down completely when the pin is HIGH. The bias circuit and comparator powers down and the reference input becomes high impedance at the end of each conversion 1000 100 10 1 0.1k 1k 10k 100k Sample Rate (kHz) T A = 25°C V CC = 5V V REF = 5V f CLK = 16 • fSAMPLE FIGURE 2. Automatic Power Shutdown Between Conver- sions Allows Power Consumption to Drop with Sample Rate. FIGURE 1. ADS1286 Operating Sequence. |
Podobny numer części - ADS1286UCG4 |
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Podobny opis - ADS1286UCG4 |
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