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ADC124S021CIMMX Arkusz danych(PDF) 2 Page - Texas Instruments |
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ADC124S021CIMMX Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 28 page IN1 IN4 MUX T/H SCLK VA GND CS DIN DOUT CONTROL LOGIC 12-Bit SUCCESSIVE APPROXIMATION ADC . . . GND 1 2 3 4 5 6 7 8 9 10 CS SCLK DOUT DIN IN1 GND IN4 IN2 VA ADC124S021 IN3 ADC124S021 SNAS277F – MARCH 2005 – REVISED MARCH 2013 www.ti.com Connection Diagram Figure 1. 10-Lead VSSOP See DGK Package Block Diagram PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 10 SCLK Digital clock input. This clock directly controls the conversion and readout processes. Digital data output. The output samples are clocked out of this pin on falling edges of the 9 DOUT SCLK pin. Digital data input. The ADC124S021's Control Register is loaded through this pin on rising 8 DIN edges of the SCLK pin. Chip select. On the falling edge of CS, a conversion process begins. Conversions continue 1 CS as long as CS is held low. POWER SUPPLY Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and 2 VA bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 3 GND The ground return for the supply and signals. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC124S021 |
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