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ADS7887 Arkusz danych(PDF) 10 Page - Texas Instruments |
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ADS7887 Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 29 page www.ti.com 1 2 3 4 5 9 10 16 CS SCLK SDO td5 td6 Invalid Data Valid Data SDO 1 5 4 3 2 6 10 9 8 7 13 12 11 16 15 14 1 5 4 3 2 6 10 9 8 7 13 12 11 16 15 14 SCLK Device Fully Powered-Up Device Starts Powering Up CS ADS7887 ADS7888 SLAS468 – JUNE 2005 Figure 4. Entering Power Down Mode A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power down mode. For the device to come to the fully powered up condition it takes 0.8 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 5. It is not necessary to continue until the 16th clock if the next conversion starts 0.8 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met. Figure 5. Exiting Power Down Mode 10 |
Podobny numer części - ADS7887_14 |
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Podobny opis - ADS7887_14 |
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