ADC12040_14 datasheet(7/30 Pages) TI1

Numer części	ADC12040

Szczegółowy opis	12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold

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Producent	TI1 [Texas Instruments]

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ADC12040

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SNAS135G – FEBRUARY 2001 – REVISED MARCH 2013

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =

+3.0V, PD = 0V, VREF = +2.0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX:

all other limits TA = TJ = 25°C

(1) (2) (3)

Typical

Units

Symbol

Parameter

Conditions

Limits (5)

(4)

(Limits)

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

VIN(1)

Logical “1” Input Voltage

VD = 5.25V

2.0

V (min)

VIN(0)

Logical “0” Input Voltage

VD = 4.75V

1.0

V (max)

IIN(1)

Logical “1” Input Current

VIN = 5.0V

10

µA

IIN(0)

Logical “0” Input Current

VIN = 0V

−10

µA

CIN

Digital Input Capacitance

5

pF

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

VDR = 2.5V

2.3

V (min)

VOUT(1)

Logical “1” Output Voltage

IOUT = −0.5 mA

VDR = 3V

2.7

V (min)

VOUT(0)

Logical “0” Output Voltage

IOUT = 1.6 mA, VDR = 3V

0.4

V (max)

VOUT = 2.5V or 5V

100

nA

IOZ

TRI-STATE Output Current

VOUT = 0V

−100

nA

+ISC

Output Short Circuit Source Current

VOUT = 0V

−20

mA (min)

−ISC

Output Short Circuit Sink Current

VOUT = VDR

20

mA (min)

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND, VREF = 2.0V

59

66

mA (max)

IA

Analog Supply Current

PD Pin = VDR

8

mA

PD Pin = DGND

6

7.3

mA (max)

ID

Digital Supply Current

PD Pin = VDR, fCLK = 0

0

mA

PD Pin = DGND, CL = 0 pF

(6)

3

mA (max)

IDR

Digital Output Supply Current

PD Pin = VDR, fCLK = 0

0

mA

PD Pin = DGND, CL = 0 pF

(7)

340

366

mW

Total Power Consumption

PD Pin = VDR, fCLK = 0

40

mW

Rejection of Full-Scale Error with

PSRR1

Power Supply Rejection

58

dB

VA = 4.75V vs. 5.25V

SNR Degradation w/10 MHz,

PSRR2

Power Supply Rejection

50

dB

200 mVP-P riding on VA

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per (). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100

mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions. See Figure 1

(2)

To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.

(4)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

(5)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

(6)

IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x

f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at

which that pin is toggling.

(7)

Excludes IDR. See previous note.

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