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ADC08DL500 Arkusz danych(PDF) 5 Page - Texas Instruments

Numer części ADC08DL500
Szczegółowy opis  ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter
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ADC08DL500 Arkusz danych(HTML) 5 Page - Texas Instruments

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50k
VA
AGND
VA
AGND
50k
Control from VCMO
VCMO
150
VA
AGND
VA
AGND
100
VBIAS
50k
50k
GND
VA
50k
50k
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Calibration Delay and Serial Interface Chip Select. With a
logic high or low on pin 16, and a logic high on pin 47, this pin
functions as Calibration Delay and sets the number of input
clock cycles after power up before calibration begins With pin
141
CalDly / SCS
16 floating, and a logic low on pin 47, this pin acts as the
enable pin for the serial interface input and the CalDly value
becomes "0" (short delay with no provision for a long power-
up calibration delay). CalDly functionality: (3)
LVDS Clock input pins for the ADC. The differential clock
20
CLK+
signal must be a.c. coupled to these pins. The input signal is
21
CLK
sampled on the falling edge of CLK+.
VINI+
VINI−
Analog signal inputs to the ADC. The differential full-scale
13
input range of this input is programmable using the FSR pin
12
16 in normal mode and the Input Full-Scale Voltage Adjust
24
register in the extended control mode. Refer to the VIN
VINQ+
25
specification in the Converter Electrical Characteristics for the
VINQ−
full-scale input range in the normal mode.
Copyright © 2011, Texas Instruments Incorporated
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