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ML22Q394 Arkusz danych(PDF) 5 Page - List of Unclassifed Manufacturers |
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ML22Q394 Arkusz danych(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 42 page FEDL22Q394-02 ML22Q394 5/42 PIN DESCRIPTION Pin Symbol I/O Initial value (At the RESET_N Input) Initial value (At standby) Description 1 SPP O Hi-Z Hi-Z Positive(+) output pin of the speaker amplifier built-in 2 SPM O Hi-Z Hi-Z Negative(-) output pin of the speaker amplifier built-in. 3 SPGND — — — Ground pin for the speaker amplifier. 4 SPVDD — — — Power supply pin for the speaker amplifier. Connect a bypass capacitor of 1 µF or more between this pin and SPGND pin. 5 BUSYB O Hi-Z 1 BUSY output pin. When BUSYB use mode is set, the "L" level is outputted during playback. At the time of a disconnection detection function, when disconnection is detected, the "L" level is outputted. In addition, when BUSYB use mode is not set, the initial value is outputted. 6 DGND — — — Digital ground pin. 7 VDDL — — — Regulator output pin for internal logic circuitry. Connect a capacitor of 10 µF or more between this pin and DGND pin 8 DVDD — — — Power supply pins for logic circuitry. Connect a capacitor of 1 µF or more between this pin and DGND pin. 9 CSB I 1 1 Chip select pin, when CSB use mode is set. At the “L” level, data input is available. When CSB use mode is not set, this pin should be fixed to “H” level od “L” level. 10 SDA I 1 1 Input pin for I2C serial data. Use for setting the mode of write and writing address, writing data. This pin should be connected to pull-up resistor. 11 SCL I 1 1 Clock input pin for I2C serial interface. This pin should be connected to pull-up resistor. 14 VPP — — — Power supply pin for rewriting Flash memory. Fix this pin to GND except when rewriting Flash memory. 15 TEST I 0 0 Test pin. Fix this pin to a DGND level. 16 RESET_N I 0 1 At the “L” level, the LSI enters initial state. After the power supply voltage is stable, drive this pin to “H” level. |
Podobny numer części - ML22Q394 |
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Podobny opis - ML22Q394 |
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