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LS833 Arkusz danych(PDF) 1 Page - Micross Components

Numer części LS833
Szczegółowy opis  Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
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Producent  MICROSS [Micross Components]
Strona internetowa  http://www.micross.com
Logo MICROSS - Micross Components

LS833 Arkusz danych(HTML) 1 Page - Micross Components

  LS833 Datasheet HTML 1Page - Micross Components  
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Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
FEATURES 
LOW DRIFT 
| V GS1‐2 / T| ≤75µV/°C 
LOW LEAKAGE 
IG = 0.5pA MAX. 
LOW NOISE 
e= 70nV/√Hz TYP. 
LOW CAPACITANCE 
CISS = 3pF MAX. 
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted) 
Maximum Temperatures 
Storage Temperature ‐65°C to +150°C 
Operating Junction Temperature 
+150°C 
Maximum Voltage and Current for Each Transistor – Note 1 
‐VGSS 
Gate Voltage to Drain or Source 
40V 
‐VDSO 
Drain to Source Voltage 
40V 
‐IG(f) 
Gate Forward Current 
10mA 
‐IG 
Gate Reverse Current 
10µA 
Maximum Power Dissipation 
Device Dissipation @ Free Air – Total                 400mW @ +125°C 
 
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL 
CHARACTERISTICS 
VALUE 
UNITS 
CONDITIONS 
| V GS1‐2 / T| max. 
DRIFT VS. 
TEMPERATURE 
75 
µV/°C 
VDG=10V, ID=30µA 
TA=‐55°C to +125°C 
| V GS1‐2 | max. 
OFFSET VOLTAGE 
25 
mV 
VDG=10V, ID=30µA 
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL 
CHARACTERISTICS 
MIN. 
TYP. 
MAX. 
UNITS 
CONDITIONS 
BVGSS 
Breakdown Voltage 
40 
60 
‐‐ 
VDS = 0                  ID=1nA 
BVGGO 
Gate‐To‐Gate Breakdown 
40 
‐‐ 
‐‐ 
      I G= 1nA               ID= 0               IS= 0 
 
YfSS 
TRANSCONDUCTANCE 
Full Conduction 
 
70 
 
300 
 
500 
 
µmho 
 
VDG= 10V         VGS= 0V      f = 1kHz 
YfS 
Typical Operation 
50 
100 
200 
µmho 
     VDG= 10V         ID= 30µA    f = 1kHz 
|YFS1‐2 / Y FS| 
Mismatch 
‐‐ 
0.6 
%  
 
IDSS 
DRAIN CURRENT 
Full Conduction 
 
0.5 
 
‐‐ 
 
10 
 
mA 
 
VDG= 10V              VGS= 0V 
|IDSS1‐2 / IDSS
Mismatch at Full Conduction 
‐‐ 
%  
 
VGS(off) or Vp 
GATE VOLTAGE 
Pinchoff voltage 
 
0.6 
 
 
4.5 
 
 
VDS= 10V               ID= 1nA 
VGS(on) 
Operating Range 
‐‐ 
‐‐ 
              VDS=10V                 ID=30µA 
 
‐IGmax. 
GATE CURRENT 
Operating 
 
‐‐ 
 
‐‐ 
 
0.5 
 
pA 
 
VDG= 10V ID= 30µA 
‐IGmax. 
High Temperature 
‐‐ 
‐‐ 
0.5 
nA 
TA= +125°C
 
‐IGSSmax. 
At Full Conduction 
‐‐ 
‐‐ 
1.0 
pA 
VDS =0 
‐IGSSmax. 
High Temperature 
1.0 
nA 
VGS= 0V, VGS= ‐20V, TA= +125°C 
IGGO 
Gate‐to‐Gate Leakage 
‐‐ 
‐‐ 
pA 
VGG = 20V 
 
YOSS 
OUTPUT CONDUCTANCE 
Full Conduction 
 
‐‐ 
 
‐‐ 
 
 
µmho 
 
VDG= 10V              VGS= 0V 
YOS 
Operating 
‐‐ 
‐‐ 
0.5 
µmho 
VDG=  10V            ID= 30µA 
 
CMR 
COMMON MODE REJECTION 
‐20 log | V GS1‐2/ V DS
 
‐‐ 
 
90 
 
‐‐ 
 
dB 
 
∆VDS = 10 to 20V        ID=30µA 
‐20 log | V GS1‐2/ V DS
‐‐ 
90 
‐‐ 
∆VDS = 5 to 10V        ID=30µA 
 
NF 
NOISE 
Figure 
 
‐‐ 
 
‐‐ 
 
 
dB 
VDS= 10V      VGS= 0V       RG= 10MΩ 
f= 100Hz           NBW= 6Hz 
en 
Voltage 
‐‐ 
20 
70 
nV/√Hz 
VDS=10V   ID=30µA   f=10Hz  NBW=1Hz 
 
CISS 
CAPACITANCE 
Input 
 
‐‐ 
 
‐‐ 
 
 
pF 
 
VDS= 10V,  VGS= 0V,  f= 1MHz 
CRSS 
Reverse Transfer 
‐‐ 
‐‐ 
1.5 
pF 
VDS= 10V,  VGS= 0V,  f= 1MHz 
CDD 
Drain‐to‐Drain 
‐‐ 
‐‐ 
0.1 
pF 
VDS= 10V,   ID=30µA 
LS833
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
LS833 Applications:
Wideband Differential Amps
High-Speed,Temp-Compensated Single-
Ended Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors.
The LS833 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS833 features a 25-
mV offset and 75-µV/°C drift.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
Available Packages:
LS833 / LS833 in P-DIP & SOIC
LS833 / LS833 available as bare die
Please contact Micross for full package and die dimensions
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
PDIP & SOIC (Top View)


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