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74VHC373SJX Arkusz danych(PDF) 5 Page - Fairchild Semiconductor |
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74VHC373SJX Arkusz danych(HTML) 5 Page - Fairchild Semiconductor |
5 / 9 page ©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC373 Rev. 1.3 5 AC Electrical Characteristics Notes: 3. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min |; tOSHL = |tPHL max – tPHL min| 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC/8 (per Latch). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) = 14 + 13n. AC Operating Requirements Symbol Parameter VCC (V) Conditions TA = +25°C TA = –40°C to +85°C Units Min. Typ. Max. Min. Max. tPLH, tPHL Propagation Delay Time (LE to On) 3.3 ± 0.3 CL = 15pF 7.0 11.0 1.0 13.0 ns CL = 50pF 9.5 14.5 1.0 16.5 5.0 ± 0.5 CL = 15pF 4.9 7.2 1.0 8.5 ns CL = 50pF 6.4 9.2 1.0 10.5 tPLH, tPHL Propagation Delay Time (D to On) 3.3 ± 0.3 CL = 15pF 7.3 11.4 1.0 13.5 ns CL = 50pF 9.8 14.9 1.0 17.0 5.0 ± 0.5 CL = 15pF 5.0 7.2 1.0 8.5 CL = 50pF 6.5 9.2 1.0 10.5 tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 RL = 1kΩ CL = 15pF 7.3 11.4 1.0 13.5 ns CL = 50pF 9.8 14.9 1.0 17.0 5.0 ± 0.5 CL = 15pF 5.5 8.1 1.0 9.5 ns CL = 50pF 7.0 10.1 1.0 11.5 tPLZ, tPHZ 3-STATE Output Disable Time 3.3 ± 0.3 RL = 1kΩ CL = 50pF 9.5 13.2 1.0 15.0 ns 5.0 ± 0.5 CL = 50pF 6.5 9.2 1.0 10.5 tOSLH, tOSHL Output to Output Skew 3.3 ± 0.3 (3) CL = 50pF 1.5 1.5 ns 5.0 ± 0.5 CL = 50pF 1.0 1.0 CIN Input Capacitance VCC = Open 4 10 10 pF COUT Output Capacitance VCC = 5.0V 6 pF CPD Power Dissipation Capacitance (4) 27 pF Symbol Parameter VCC (V) TA = +25°C TA = –40°C to +85°C Units Min. Typ. Max. Min. Max. tW(H) Minimum Pulse Width (LE) 3.3 ± 0.3 5.0 5.0 ns 5.0 ± 0.5 5.0 5.0 tS Minimum Set-Up Time 3.3 ± 0.3 4.0 4.0 ns 5.0 ± 0.5 4.0 4.0 tH Minimum Hold Time 3.3 ± 0.3 1.0 1.0 ns 5.0 ± 0.5 1.0 1.0 |
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